2009
DOI: 10.1016/j.microrel.2009.07.016
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A new built-in screening methodology to achieve zero defects in the automotive environment

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Cited by 10 publications
(5 citation statements)
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“…The main issue of the traditional DLT is related to the fact that this procedure can only be carried out if the direct access to the drain contact is directly (and separately) ensured [11]. Actually, the direct contact to the drain contact of LDMOS is just granted through the pins if they are used to drive external loads.…”
Section: ) Traditional Screening Procedures For Stimentioning
confidence: 99%
See 1 more Smart Citation
“…The main issue of the traditional DLT is related to the fact that this procedure can only be carried out if the direct access to the drain contact is directly (and separately) ensured [11]. Actually, the direct contact to the drain contact of LDMOS is just granted through the pins if they are used to drive external loads.…”
Section: ) Traditional Screening Procedures For Stimentioning
confidence: 99%
“…A detailed description of the circuit implementing the concept together with circuit simulation results can be found in [11].…”
Section: ) Working Principlementioning
confidence: 99%
“…Later, the modifications that are needed to add the built-in DLT (BI-DLT) functionality in the existing circuits have been presented [8]. Finally, a new procedure has been prototyped and validated experimentally after integrating both functionality in a test chip [9].…”
Section: New Built-in Defect-based Techniquementioning
confidence: 99%
“…Advantages of the BI-DLT: The BI-DLT provides major advantages either as a stand-alone screening technique or in conjunction with a traditional burn-in procedure [8]. The design solution proposed here for the stand-alone version refers to an LS switch with direct access to the drain and source through external pins.…”
Section: A Working Principlementioning
confidence: 99%
“…Screening Methodologies. Nowadays, the most common procedure to screen gate oxide defects at chip level is still the so-called gate stress test (GST), where a high voltage pulse is applied through an Automatic Test Equipment (ATE) to dedicated test pads of the LDMOS gate [5]. Subsequently, the eventual occurrence of the oxide breakdown is detected by the measurement of the leakage current through the gate oxide.…”
Section: Introductionmentioning
confidence: 99%