A new architecture of median filters with linear hardware complexity

Abstract

This paper proposes a new algorithm of median filters for VLSI implementation. The architecture based on this algorithm has modular, regular, locally connected and expansible features. The throughput of the filter is independent of the window size and the hardware complexity is O(WN), where W is the window size and N is the bit number per pixel.

High Throughput VLSI Architecture for One Dimensional Median Filter

“…The technology independent results of proposed architecture is presented in terms of gate delay in Table-II which is critical delay and vital for high throughputs. The critical delay, in terms of number of 2-input gate delays is much better than the results presented in [11]. The critical path delay in terms of gate delay increases by two with doubling of word size.…”

“…The beauty of this comparator design is that whenever number of bit are doubled, the critical path increases by just one merging circuit which is 2 gate plus one inverter delays as in Fig 4(b). This design is much better than the one used in [11].…”

“…The fastest method of sorting is to perform multiple actions (addition and deletion of elements) at the same time [11,12]. We describe these operations as given here, when values are input in a serial order, into the median filter, we can maintain two arrays, one called window array which contains input elements and second one is called sorted array, which contains window elements in sorted fashion(ascending/descending).…”

“…Here we have designed the circuits for each block and integrated to a final architecture using parallel and pipelined techniques to have lesser critical delay and thus to achieve high throughput. The comparator stage shown in Fig.2, happens to be the critical path in [11] with an 8bit comparator taking 15gate delays. So to get the fastest filter, we need optimization of the circuit of this stage.…”