A new approach to power estimation and reduction in CMOS digital circuits

Brzozowski, Ireneusz; Kos, Andrzej

doi:10.1016/j.vlsi.2007.06.003

Cited by 11 publications

(8 citation statements)

References 9 publications

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“…Authors used extended power model, which based on gates driving way [6], for power estimation accuracy improvement. This power model consists in taking into account changes of input vectors.…”

Section: A Energy Parametersmentioning

confidence: 99%

Designing Method of Compact n-to-2n Decoders

Brzozowski¹,

Zachara²,

Kos³

2013

International Journal of Electronics and Telecommunications

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Abstract-What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to-2 n -lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.

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Section: A Energy Parametersmentioning

confidence: 99%

Designing Method of Compact n-to-2n Decoders

Brzozowski¹,

Zachara²,

Kos³

2013

International Journal of Electronics and Telecommunications

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“…Moreover energy is consumed even when the gate output does not change its logical value when inputs change. In order to modeling these dependencies the new model of power consumption has been developed [5], [6], [7]. And a new measure of a circuit activity -gate driving way -has been introduced.…”

Section: B New Model Of Power Dissipationmentioning

confidence: 99%

“…And a new measure of a circuit activity -gate driving way -has been introduced. So, power consumption dependences on a reason of the gate switching were shown in [5], [6], [7].…”

Section: B New Model Of Power Dissipationmentioning

confidence: 99%

“…For power estimation more useful is probability parameter representing a circuit activity. So, the gate driving way probability is defined as probability of the occurrence of the particular gate driving way [6], [7], [8]. The definition includes no change cases and therefore sum of probabilities for all driving ways is one.…”

Section: B New Model Of Power Dissipationmentioning

confidence: 99%

“…The new model of power is used in power estimation and optimization procedures [6], [7] [8]. Above defined gate driving way probability is treated as a coefficient, which describe participation of driving way dependent equivalent capacitance in a total gate power dissipation.…”

Section: B New Model Of Power Dissipationmentioning

confidence: 99%

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Calculation methods of new circuit activity measure for low power modeling

Brzozowski

Kos

2008

2008 International Conference on Signals and Electronic Systems

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Calculation procedures for the gate driving way probability -the new measure of a circuit activity, developed for low power modeling -are presented in this paper. The new model of power dissipation, using the measure, has improved estimation accuracy. Moreover, it allows developing of new methods for low power design. The gate driving way can be easy calculated using logic simulations, but it is time-consuming method. So, the authors propose efficient and fast calculation procedures. The versatile algorithm for any circuit has been developed as well as very fast one for two-level circuits only. Results of new algorithms using were compared for a set of MCNC benchmark circuits.

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Designing of low-power data oriented adders

Brzozowski

Kos

2014

Microelectronics Journal

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A new approach to power estimation and reduction in CMOS digital circuits

Cited by 11 publications

References 9 publications

Designing Method of Compact n-to-2n Decoders

Designing Method of Compact n-to-2n Decoders

Calculation methods of new circuit activity measure for low power modeling

Designing of low-power data oriented adders

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