A new approach for the design of linear systolic arrays for computing third-order cumulants

Efficiency of Priority Queue Architectures in FPGA

“…Many architectures exist for sorting data in priority queues while keeping instruction response times constant. FIFO with MUX Trees [2,3], Shift Registers [4,5], DP RAM Heapsort [6], Systolic Array [8,9], Rocket Queue [16], and Heap Queue [17] are among the most popular architectures.…”

“…The first cell from the right is the first cell in the queue, also serving as an external interface. Only clock and reset signals are propagated in parallel [8,9]. While Shift Registers architecture applies instruction to all cells in parallel via shared bus, the Systolic Array architecture gives the instruction to move sequentially, from the first cell to the last cell, at a speed of one cell per clock cycle.…”

“…Even though this sequential processing might sound like a performance drawback, the instructions can be pipelined, maintaining high throughput. Since the output of this priority queue is obtained from the first cell, this output is updated already at the first cycle of instruction, providing the same instruction latency as Shift Registers architecture (one clock cycle) [8,9]. Figure 2 illustrates the Systolic Array architecture with four cells.…”

“…The first cell from the right is the first cell in the queue, also serving as an external interface. Only clock and reset signals are propagated in parallel [8,9]. In the Systolic Array, each cell represents a pipeline stage, including the pipeline register.…”

“…In the past, several hardware architectures have been developed for data sorting or prioritizing information, but they are largely limited by their logical resources; especially when multiple such priority queues are required, they may have overly high chip area costs in ASIC and high LUTs consumption in FPGA technologies [2][3][4][5][6][7][8][9][10][11][12][13].…”