A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms

Timmermann, Dirk; Hahn, Hernsoo; Hosticka, B.J.; Rix, B.

doi:10.1016/0167-9260(91)90008-9

Cited by 34 publications

(11 citation statements)

References 16 publications

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“…A comparison of several scale factor compensation techniques proposed in the literature along with two additional methods, additive and multiplicative decomposition approaches, for radix-2 CORDIC is presented in [44]. It is observed from the presented results that additive technique offers a low latency solution and multiplicative technique offers an area economical solution for applications of CORDIC employing array and pipelined architectures.…”

Section: Scale Factor Compensationmentioning

confidence: 94%

“…For the microrotations in the range i ≥ (n/6), the σ i values are predicted from the the remaining angle after the first n/6 [60]. Thus, the complexity of the w path is n/6, compared to n in the other architectures [42][43][44][45][46][47][48][49][50][51][52][53] presented in the previous sections. For the range 0 ≤ i < (n/6), microrotations are pipelined in two stages to increase the throughput.…”

Section: Redundant Radix 2-4 Cordicmentioning

confidence: 99%

“…On an average, the number of nonzero digits can be reduced to n/3 using CSD representation [32] and hence, the effort for multiplication using CSD recoded multiplier is approximately one third that required using conventional multiplier. Further, scaling can also be implemented using a Wallace tree by fully parallelizing multiplication and is preferred for applications aiming for low latency at the expense of more silicon area [44].…”

Section: Scale Factor Compensationmentioning

confidence: 99%

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CORDIC Architectures: A Survey

Boppana

Dhar

2010

VLSI Design

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In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.

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Section: Scale Factor Compensationmentioning

confidence: 94%

Section: Redundant Radix 2-4 Cordicmentioning

confidence: 99%

Section: Scale Factor Compensationmentioning

confidence: 99%

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CORDIC Architectures: A Survey

Boppana

Dhar

2010

VLSI Design

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“…Several methods to avoid performing the final product by K m -1 and carry out the scaling compensation in parallel with each of the iterations have been proposed [17]- [20].…”

Section: A Reviewing the Binary Cordic Methodsmentioning

confidence: 99%

A high performance architecture for rotating decimal coordinates

Sánchez

Mora

et al. 2008

2008 IEEE International Symposium on Industrial Electronics

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Abstract-Although radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are still under development. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to produce fast rotations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations in comparison to the original decimal CORDIC method is achieved. The experiments showing the advantages of the new method are described. Finally, the results with regard to delay obtained by means of an FPGA implementation of the method are shown.

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“…Generalized algorithms, and their corresponding architectures to perform the scale-factor compensation in parallel with the CORDIC iterations, for both rotation and vectoring modes are proposed in [60], where the compensation overhead is reduced to a couple of iterations. It is shown in [61] that since the scale-factor is known in advance, one can perform the minimal recoding of the bits of scaling-factor, and implement the multiplication thereafter by a Wallace tree. It is a good solution of low-latency scaling particularly for pipelined CORDIC architectures.…”

Section: B Low-complexity Scalingmentioning

confidence: 99%