A new 21-level asymmetrical multilevel inverter topology with different PWM techniques

Amesur, Nikhil B.; Bansal, Praveen

doi:10.1109/rdcape.2017.8358271

Cited by 17 publications

(10 citation statements)

References 4 publications

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“…Figure 2 illustrates the suggested bottom inverter's operating modes, comprising four IGBT switches and two bidirectional switches. The green color indicates the conduction of switches and capacitors [25].…”

Section: Modes Of Operationmentioning

confidence: 99%

Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches

Alghaythi,

Irudayaraj,

Ramu

et al. 2023

Sustainability

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The multilevel inverter (MLI) has been developed as a powerful power conversion scheme for several processes, including renewable energy, transmission systems, and electric drives. It has become popular across medium- to high-power operations due to its many advantages, including minimum harmonic content, low switching losses, and reduced electromagnetic interference (EMI). In this paper, the capacitor voltage balancing technique-based pulse width modulation (PWM) has been proposed. The proposed PWM strategy offers several advantages, such as high-quality output waveforms with reduced harmonic distortion, improved efficiency, and better control over the output voltage. The Xilinx ISE 10.1 software was used for synthesizing, and the VHDL code was written for the proposed method. MATLAB software was used to simulate and hardware was used to verify the proposed system. The SPARTAN 3E FPGA was used for the generation of the PWM. This paper developed a 2 kW single-phase 15-level inverter that created an AC wave from the DC input voltage, with a total harmonic distortion (THD) of 8.02%, which was less than the THD achieved from other conventional MLI. The results indicate that MLI topologies with low total harmonic currents, fewer switches, and higher output voltage levels are better stabilized during load disturbance circumstances.

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Section: Modes Of Operationmentioning

confidence: 99%

Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches

Alghaythi,

Irudayaraj,

Ramu

et al. 2023

Sustainability

View full text Add to dashboard Cite

show abstract

“…A combination of switches is turned ON for producing a positive voltage and negative voltages [15]. The asymmetric topology is also capable of producing higher levels of voltage, as explained by the authors in [16]. The authors analyzed a 21-level MLI made up of a full bridge converter with semiconductor switches and different voltage sources.…”

Section: Asymmetric Multilevel Invertermentioning

confidence: 99%

An Extensive Review of Multilevel Inverters Based on Their Multifaceted Structural Configuration, Triggering Methods and Applications

2020

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Power electronic converters are used to transform one form of energy to another. They are classified into four types depending upon the nature of the input and output voltages. The inverter is one among those types; it converts direct electrical current into alternating electrical current at desired frequency. Conventional types of inverters are capable of producing voltage at the output terminal that can only switch between two levels. The range of output voltage generated at the output is low when they are used for high power applications. To improve the voltage profile and efficiency of the overall system, multilevel inverters (MLIs) are introduced. In multilevel inverters the voltage at the output terminal is generated from several DC voltage levels fed at its input. The generated output is more appropriate to a sine wave and the dv/dt rating is also less leading to the reduction in EMI. Though they possess many advantages compared to the conventional inverters, the structural complexity and triggering techniques involved in designing multilevel inverters are high. Many studies are being carried out in defining new topologies of MLI with reduced switch as well as with the implementation of different PWM techniques. This paper will provide an extensive review on variety of MLI configurations based on the parameters such as the number of switches, switching techniques, symmetric, asymmetric, hybrid topologies, configurations based on applications, THD and power quality.

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“…Over the last decade, multilevel inverters (MLIs) have garnered significant research attention in high-voltage and high-power applications, such as high-power motor drives, power conditioning, renewable energy conversion, and power distribution, due to their simple structure, modularity, and transformer-less circuit [1][2][3][4]. The primary role of a multilevel inverter is to convert direct current (DC) input to alternating current (AC) output by generating a staircase of AC output waveforms with a low value of high-frequency distortion [4,5].…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model

et al. 2022

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Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (± 360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

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A new 21-level asymmetrical multilevel inverter topology with different PWM techniques

Cited by 17 publications

References 4 publications

Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches

Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches

An Extensive Review of Multilevel Inverters Based on Their Multifaceted Structural Configuration, Triggering Methods and Applications

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model

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