A Neutron Activation Analysis Study of the Sources of Transition Group Metal Contamination in the Silicon Device Manufacturing Process

Abstract

A survey is given of the sources, species, and quantities of transition group metals residing on starting silicon substrates and introduced during the device manufacturing process. The survey begins with the polysilicon feed for silicon ingot fabrication and extends through all customary device fabrication steps, such as wafering, polishing, oxidations, epitaxy, ion implantation, etc. High temperature furnace operations in the absence of HC1, such as steam oxidations, are presently the major source of contamination if all other steps of the fabrication process are under full control. However, contaminated polishing slurries, contaminated handling tools or carriers, impure SiC boats or susceptors, or choice of unsuitable materials for beam catcher plates, etc. in ion implantation, can also lead to trouble. Several options are available to avoid the contamination introduced during high temperature treatments, and these are reviewed. * Electrochemical Society Active Member.

Fabrication of monolithic photovoltaic arrays on crystalline silicon by wafer bonding and deep etching techniques

“…It is well known that contamination in the high temperature steps might degrade the bulk lifetime and hence the photovoltaic efficiency. 20,21 Besides, rear passivation is poor due to the silicon fusion bonding procedure. 23 Standard measurements of photovoltaic devices involve current-voltage characteristics measured under standard solar spectrum AM1Á5, 100 mW/cm 2 , 25 C. Photovoltaic minimodules fabricated by the two approaches described above have been systematically measured under standard conditions.…”

“…8,13 The results obtained so far are in general promising, but many problems remain as the efficiencies reported are much lower than state of the art technology for individual cells. This is due to a number of reasons: poor isolation between contiguous solar cells, 11 lifetime degradation during array processing, 20,21 poor surface passivation, high series resistance due to interconnects and faulty devices due to unwanted shunts or open circuits. Most of the monolithic solutions based on c-Si shown in the literature 11 have areas in the range of 10 cm 2 , while designs based on a-Si 6,18 show areas of 1 mm 2 or 1 cm 2 .…”

Análise da passivação com SiO 2 na face posterior e frontal de células solares com campo retrodifusor seletivo

“…Isso explica o aumento da V OC no intervalo de temperatura de 770 °C ≤ T oxi ≤ 860 °C. No entanto, para temperaturas de oxidação maiores que este valor, provavelmente a qualidade da passivação mantém-se, porém a lâmina de silício sofre contaminação ou criam-se defeitos que reduzem o tempo de vida dos portadores minoritários na base [27]. Ao mesmo tempo, o emissor torna-se mais profundo e aumenta a região altamente dopada, aumentando a recombinação dos minoritários.…”

Desenvolvimento de células solares em silício tipo n com emissor formado por Boro

“…No entanto, tempos de vida de minoritários da ordem de 116 µs, em lâminas tipo n com resistividade de aproximadamente 9 Ω.cm, apresentam comprimentos de difusão de 374 µm, maior que a espessura da lâmina. Também se observou que quanto maior a temperatura do processo de difusão de boro, menor foi o tempo de vida medido para os minoritários, característica típica de processos com contaminação e que indica que este processo é o principal redutor deste parâmetro [21]. A resistência de folha da região p + em função da temperatura é apresentada na Figura 3, onde se observa o rápido decrescimento deste parâmetro quando a temperatura aumenta de 900 ºC para 1020 ºC.…”