A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks

Abstract-We present a compact circuit architecture for analog VLSI realization of event-addressable neuromorphic arrays with conductance-based synaptic dynamics. Synaptic input events are time-multiplexed, pooled by synapse type according to common reversal potential and activation dynamics. One such physical synapse element per postsynaptic neuron is provided for each type, selected by type index along with postsynaptic address. A log-domain encoding of first-order linear dynamics of synaptic conductance results in a compact circuit realization with three MOS transistors per synapse element. Circuit simulations show low-power operation with linear dynamics in conductance.

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Finding a roadmap to achieve large neuromorphic hardware systems

Hasler

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks

Cited by 5 publications

References 74 publications

Neuromorphic Cognition

Neuromorphic Cognition

Log-Domain Time-Multiplexed Realization of Dynamical Conductance-Based Synapses

Finding a roadmap to achieve large neuromorphic hardware systems

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