A networks-on-chip architecture design space exploration – The LIB

Liu, Peng; Xia, Bingjie; Xiang, Chunchang; Wang, Xiaohang; Wang, Weidong; Yao, Qingdong

doi:10.1016/j.compeleceng.2008.11.027

Cited by 12 publications

(4 citation statements)

References 20 publications

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“…If the on-chip network possesses of the same characteristics, the RIP can be reused as well. Therefore, the authors suggest building a library consisting of components compatible with prevalent protocols (Liu et al, 2009). NoC designers can choose the optimum components from the library to construct their specified NI as illustrated in Figure 7.…”

Section: Ni Component Librarymentioning

confidence: 99%

Network interface design based on mutual interface definition

Xia

Xiang³

et al. 2010

IJHPSA

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This paper proposes a novel network interface design method, referred to as mutual interface definition based method. It decouples resource dependent part (RDP) from resource independent part (RIP) by mutual interface definition. These two parts can be designed independently, thus the design flexibility and reusability of network interface can be enhanced. Moreover, a network interface component library consisting of multiple RDP and RIP components is proposed to be built. The networks-on-chip designers can choose appropriate components from the library to construct network interface design. From the perspective of RDP, the network interface achieves backward compatibility with the existing protocols such as AMBA AHB and OCP. From the perspective of RIP, the network interface provides a configurable structure supporting multicast transfer and adaptive routing algorithm extensions. The proposed network interface designs are implemented in TSMC 90-nm CMOS standard cell technology and can work at the frequency of 1.12 GHz to 1.35 GHz.

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Section: Ni Component Librarymentioning

confidence: 99%

Network interface design based on mutual interface definition

Xia

Xiang³

et al. 2010

IJHPSA

Self Cite

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“…NoC is a communication network between multiple devices. Devices are connected in regular or irregular topology [7][8][9]. The devices are processor, memory, DSP core etc are called processing element (PE).…”

Section: Fig (1) Interconnection System Of Socmentioning

confidence: 99%

Review of Network on Chip Routing Algorithms

Ahmad¹,

Sethi²

2020

EAI Endorsed Transactions on Context-aware Systems and Applicat

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“…Moreover, multiprocessor SoC (MPSoC) was also not able to handle the globally asynchronous locally synchronous (GALS) communication. Researchers and scientists have started thinking about the alternate concept of NoC, as it provides the modularity, scalability, and efficient reuse of resources while meeting the high bandwidth, throughput, and low‐latency communication requirements . In NoC, the cores can be connected by any regular or irregular topology.…”

Section: Introductionmentioning

confidence: 99%

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Sethi

Hussin

Hamid

2018

IEEJ Transactions Elec Engng

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Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques.

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A networks-on-chip architecture design space exploration – The LIB

Cited by 12 publications

References 20 publications

Network interface design based on mutual interface definition

Network interface design based on mutual interface definition

Review of Network on Chip Routing Algorithms

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

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