A nanowire-based shift register for display scan drivers

Abstract

The development of display scan drivers is an essential step in the effort to develop transparent and flexible display devices based on nanowire transistors. Here we report a transparent nanowire-based shift register that functions as the standard logic circuit of a display scan driver. To form the shift register circuits using only n-type nanowire transistors, a novel circuit structure was introduced to avoid the output voltage drop typical of purely n-type circuits. A circuit simulation based on the measured nanowire transistor characteristics was developed in the planning phase to verify the circuit operation of the shift register. The shift register successfully produced an output of 0-3 V without an output voltage drop while applying an input of 3 V peak to peak. In addition, the shift register was designed to have multiple channels with a randomly oriented nanowire placement method to enhance the operation yield.

A Low-Output-Noise Multistage Shift Register Using Tin Dioxide Nanowire Transistors

“…3, the voltage level of V N and V N +1 is up to 4.89 V. The output noise is under 160 mV when the voltage of V N −1 is low level and the voltage of CLKa or CLKb becomes high level. The output noise of the proposed circuit is 20% lower than that of the previous circuit [8]. Because the yield of a nanowire transistor without the parallel connection technique is 50% [8], the multistage shift register is hardly implemented.…”

“…The output noise of the proposed circuit is 20% lower than that of the previous circuit [8]. Because the yield of a nanowire transistor without the parallel connection technique is 50% [8], the multistage shift register is hardly implemented. To improve the yield of the multistage register, we used a parallel connection technique.…”

“…2 shows the measured transfer characteristic of the SnO 2 nanowire transistor under the stress condition when the diameter, the length, and the drain-to-source voltage of the SnO 2 nanowire transistor are 60 nm, 10 μm, and 0.5 V, respectively. We assumed that the number of nanowires in the channel region of the nanowire transistor is two and used the dc model with a cylindrical channel structure of the SnO 2 nanowire [8]. The transfer characteristics of the nanowire transistor are measured under the stress conditions, which are the gate-to-source voltage of 10 V, the drain-to-source voltage of 0.5 V, and the stress times of 0, 100, 200, and 300 s. The threshold voltage, the subthreshold slope, and the field-effect mobility of the SnO 2 nanowire transistor without bias stress are 0.83 V, 0.48 V/dec, and 43.6 cm 2 /(V · s), respectively.…”

“…The randomly oriented nanowire placement process [8], which is one of the methods for fabricating nanowire transistors, is a good choice to fabricate nanowire transistors on display panel because the randomly oriented nanowire placement process is free from fabrication temperature and panel size as the grown nanowire is dispersed on the panel.…”

“…A wide-channel-width and thin gate insulator causes the large gate-to-drain capacitance of the transistor. In the previously reported shift register circuit [8], the output signal has large fluctuation noise because the clock signal makes coupling noise through this large gate-to-drain capacitance of the pull-down transistor to the output node. Furthermore, it is difficult to apply the randomly oriented nanowire placement process for multistage scanning circuit in display systems because the entire multistage circuit malfunctions if a single stage circuit among them is a failure.…”