A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs

Tsuruya, Yumiko; Hirose, Takahisa; Osaki, Yuji; Kuroki, Nobutaka; Numa, Masahiro; Kobayashi, Osamu

doi:10.1109/esscirc.2012.6341258

Cited by 11 publications

(9 citation statements)

References 9 publications

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“…Table 3 shows the performance comparison of this study with other similar works i.e., Tsuruya et al (2012), Vu Cao et al (2010, Valero et al (2012), Galan et al (2007), Degrauwe et al (1982), Xing et al (2009) and Ozaki et al (2015). Our proposed amplifier achieved low power and high speed in comparison with the previous works.…”

Section: Discussionmentioning

confidence: 60%

“…Adaptive biasing circuit is a great candidate to improve stability and gain of the analogue amplifiers. The proposed amplifier is introduced in (Tsuruya et al, 2012). The amplifier has three main sections including differential pair input stage, Current Monitor Circuit (CMC), Current Comparison Circuit (CCC) and Current Amplication Circuit (CAC) (Fig.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive Biasing Low Power Amplifier Using CMOS Technology

Ghamsari¹,

Pirmoradia²

2015

J. of Applied Sciences

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A B S T R A C T In this study, an adaptive biasing CMOS operational amplifier is presented which operates at 3 V power supply and simulated at 180 and 90 nm technologies. The adaptive biasing current circuit controls the input voltages and supplies the amplifier with biasing current in order to achieving stability and optimum power consumption at higher speed. The circuit is simulated in Hspice software environment and the performance results demonstrate that the amplifier with the ABCC can operate with low power and achieve high speed of 0.012 V/us at the time rise and 0.011 V/us at fall time when the input pulse frequency and the amplitude are 1 kHz and 1.3 V peak to peak, respectively. The gain and phase margin are 35 dB and 62° at 90 nm technology, respectively.

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Section: Discussionmentioning

confidence: 60%

Section: Introductionmentioning

confidence: 99%

Adaptive Biasing Low Power Amplifier Using CMOS Technology

Ghamsari¹,

Pirmoradia²

2015

J. of Applied Sciences

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“…Dynamical/adaptive biasing techniques have been proposed before in literature, one example can be found in [12]. To our knowledge, here it is the first time that the dynamical biasing techniques are applied to the current feedback amplifier.…”

Section: B Signal Dependent Biasingmentioning

confidence: 99%

A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier with Signal Dependent Power Consumption for Fetal ECG Monitoring

et al. 2016

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• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Song, S., Rooijakkers, M. J., Harpe, P., Rabotti, C., Mischi, M., Van Roermund, A. H. M., & Cantatore, E. (2016). A noise reconfigurable current-reuse resistive feedback amplifier with signal-dependent power consumption for fetal ECG monitoring. IEEE Sensors Journal, 16(23),[8304][8305][8306][8307][8308][8309][8310][8311][8312][8313]. DOI: 10.1109/JSEN.2016 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-This paper presents a noise-reconfigurable resistive feedback amplifier with current-reuse technique for fetal ECG monitoring. The proposed amplifier allows for both tuning of the noise level and changing the power consumption according to the signal properties, minimizing the total power consumption while satisfying all application requirements. The amplifier together with its amplitude detector and dynamical biasing circuit are implemented in a standard 0.18µm CMOS process. Measurements demonstrate that the proposed current-reuse resistive feedback topology improves the power efficiency of the conventional resistive feedback amplifier, achieving at the same time a good noise efficiency factor (NEF=2.8) and an input impedance of 20MOhm. The amplitude detector and dynamical biasing circuit, which tunes the current in the amplifier according to the signal amplitude, save up to 40% of the total power consumption. The amplifier achieves a measured noise level of 0.34µVrms in a 0.6 to 175Hz band, consuming 6.3µW power.

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“…Ultra-low-power (ULP) circuit design techniques are strongly required to realize next-generation internet of things=everything (IoT=IoE) devices. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] Small rechargeable batteries are good candidate energy storage devices for ULP IoT devices. However, because the nominal voltage of these batteries is high (e.g., >3.0 V), [16][17][18][19] the power dissipation of circuits directly powered by these batteries is large.…”

Section: Introductionmentioning

confidence: 99%

A fully integrated, wide-load-range, high-power-conversion-efficiency switched capacitor DC–DC converter with adaptive bias comparator for ultra-low-power power management integrated circuit

Asano

Hirose

Kojima

et al. 2018

Jpn. J. Appl. Phys.

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In this paper, we present a wide-load-range switched-capacitor DC-DC buck converter with an adaptive bias comparator for ultra-low-power power management integrated circuit. The proposed converter is based on a conventional one and modified to operate in a wide load range by developing a load current monitor used in an adaptive bias comparator. Measurement results demonstrated that our proposed converter generates a 1.0 V output voltage from a 3.0 V input voltage at a load of up to 100 µA, which is 20 times higher than that of the conventional one. The power conversion efficiency was higher than 60% in the load range from 0.8 to 100 µA.

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A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs

Cited by 11 publications

References 9 publications

Adaptive Biasing Low Power Amplifier Using CMOS Technology

Adaptive Biasing Low Power Amplifier Using CMOS Technology

A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier with Signal Dependent Power Consumption for Fetal ECG Monitoring

A fully integrated, wide-load-range, high-power-conversion-efficiency switched capacitor DC–DC converter with adaptive bias comparator for ultra-low-power power management integrated circuit

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