A multithreaded PowerPC processor for commercial servers

Collins

SIGOPS Oper. Syst. Rev.

et al. 2004

Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run "assist" threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium r 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload. † Dongkeun Kim is currently a Ph.D. candidate in the Department of Electrical and

Section: Related Workmentioning

confidence: 99%

Helper threads via virtual multithreading on an experimental itanium ^® 2 processor-based platform

Collins

SIGOPS Oper. Syst. Rev.

et al. 2004

Advances in Computer Systems Architecture

“…SMT, while adding hardware complexity, is an established approach [22], and there are existing implementations [5].…”

Section: Future Workmentioning

confidence: 99%

L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy

Machanick

Patel

2003

The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, and uses the TLB to cache page translations in that main memory. Earlier RAMpage evaluation used a relatively small L1 cache and TLB. For the RAMpage hierarchy, the effect of a small TLB is clearer than with a conventional hierarchy, because it is more feasible to make a TLB which maps a high fraction of main memory pages. This paper illustrates how more aggressive components higher in the memory hierarchy make time spent waiting for DRAM more significant as a fraction of total execution time, and, hence, approaches to hide the latency of DRAM become more important. For an instruction issue rate of 1 GHz, the simulated standard hierarchy waited for DRAM 10% of the time; with the instruction issue rate increased to 8 GHz, the fraction of time spent waiting for DRAM increased to 40%, and was higher for a larger L1 cache. The RAMpage hierarchy with context switches on misses was able to hide almost all DRAM latency. Increasing the processor speed in a standard hierarchy by a factor of 8 and increasing L1 cache size by a factor of 16, with DRAM speed unchanged, resulted in a speedup of 6.12. Adding the RAMpage model and introducing context switches on misses, with similar processor speed and L1 improvements, resulted in a speedup of 10.7 over the slowest conventional hierarchy, or 1.74 for the best case of the conventional hierarchy with the fastest processor. A larger TLB was shown to increase the viable range of RAMpage SRAM page sizes.

Proceedings of the 26th ACM International Conference on Supercomputing

“…We leverage the IBM POWER7 hardware thread prioritization [2,5,28] to dynamically partition hardware resource (e.g., renaming registers or load/store queue entries) between the running threads.…”

Section: Introductionmentioning

confidence: 99%

Enhancing the performance of assisted execution runtime systems through hardware/software techniques

Kestor

Gioiosa

Unsal

et al. 2012

To meet the expected performance, future exascale systems will require programmers to increase the level of parallelism of their applications. Novel programming models simplify parallel programming at the cost of increasing runtime overheard. Assisted execution models have the potential of reducing this overhead but they generally also reduce processor utilization.We propose an integrated hardware/software solution that automatically partition hardware resources between application and auxiliary threads. Each system level performs well-defined tasks efficiently: 1) the runtime system is enriched with a mechanism that automatically detects computing power requirements of running threads and drives the hardware actuators; 2) the hardware enforces dynamic resource partitioning; 3) the operating system provides an efficient interface between the runtime system and the hardware resource allocation mechanism. As a test case, we apply this adaptive approach to STM 2 , an software transactional memory system that implements the assisted execution model.We evaluate the proposed adaptive solution on an IBM POWER7 system using Eigenbench and STAMP benchmark suite. Results show that our approach performs equal or better than the original STM 2 and achieves up to 65% and 86% performance improvement for Eigenbench and STAMP applications, respectively.