A multiple modulator fractional divider

Analog Integr Circ Sig Process

Wang

2006

Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigmadelta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the inband phase noise reduction of the sigma-delta frequency synthesizer.

Section: Simple Model Of Charge Pump With Mismatchmentioning

confidence: 99%

“…The sigma-delta fractional-N phase locked loop (PLL) frequency synthesizers [1,2] are widely used in all kinds of circuits ( Fig. 1).…”

Section: Introductionmentioning

confidence: 99%

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Analog Integr Circ Sig Process

Wang

2006

“…According to the quantization noise transfer function, we divide the SDM into four types. The first type is in cascaded topology, such as MASH-1-1-1 [1] , MASH-1-2 [5] , and MASH-2-1 [6] shown in Figs.1(a), 1(b), and 1(c), respectively, and a single stage multi feedback SDM proposed in Ref. [7].…”

Section: Digital Modulator Topology Overviewmentioning

confidence: 99%

“…To solve this pair of contradictory requirements, the fractional-N frequency synthesizer is proposed and it has become more and more popular in recent years. The fractional-N divider is realized by means of changing the divisor between two adjacent integers, say N and N+1 or N−1 and N, to get an average fractional 1 [2] in order to shape the dynamic-divisor imported noise. Now this method has gained a variety of applications ranging from accurate frequency generation and timing in digital systems to direct frequency modulation in radio-frequency analog front ends of modern communication systems [3] .…”

Section: Introductionmentioning

confidence: 99%

Comparison of Sigma-Delta Modulator for fractional-N PLL frequency synthesizer

Wang

2007

J. of Electron.(China)

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM, which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Multistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed, which balances the requirements of tone-free and maximum operation frequency.

“…Sigma-delta fractional-N phase-locked loop (PLL) frequency synthesizers [1,2] are widely used in a variety of applications ranging from accurate frequency generation to direct frequency modulation in high-speed communication systems such as Ethernet receivers and RF wireless communication receivers in which low jitter and fast locking time are required.…”

Section: Introductionmentioning

confidence: 99%

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

Zhao

Analog Integr Circ Sig Process

et al. 2008

A 1.41-1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 lm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is -121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is -113 dBc/Hz at 1.0 MHz.