A Multicore Processor for Time-Critical Applications

Schoeberl, Martin; Pezzarossa, Luca; Sparsø, Jens

doi:10.1109/mdat.2018.2791809

Cited by 14 publications

(15 citation statements)

References 11 publications

(14 reference statements)

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“…The proposed TTEthernet node is based on the Patmos timepredictable processor [17] used in the T-CREST platform [6], [16] and on an open-source Ethernet controller. The controller is based on the EthMac block from OpenCore [13], which was previously ported for Patmos [14].…”

Section: A Platformmentioning

confidence: 99%

A Time-predictable TTEthenet Node

Lund

Pezzarossa

Sparsø

et al. 2019

2019 IEEE 22nd International Symposium on Real-Time Distributed Computing (ISORC)

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Distributed real-time systems need time-predictable computation and communication to facilitate static analysis of timing requirements and deadlines. This paper presents the implementation of a deterministic network protocol, TTEthernet, on the time-predictable Patmos processor. The implementation uses the existing Ethernet controller on the processor and we tested it with a TTEthernet system provided by TTTech Inc. Further testing showed that the controller could send timetriggered messages with bounded latency and a small jitter of approximately 4.5 us. We also provide worst-case execution time analysis of the network code, which demonstrates a timepredictable end-to-end solution. This work enables Patmos to communicate with other nodes in a deterministic way. Thus, extending the possible uses of Patmos.

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Section: A Platformmentioning

confidence: 99%

A Time-predictable TTEthenet Node

Lund

Pezzarossa

Sparsø

et al. 2019

2019 IEEE 22nd International Symposium on Real-Time Distributed Computing (ISORC)

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“…For Patmos, we have two WCET analysis tools available: aiT [10] tool from AbsInt and the open-source tool platin [11], which allow static computation of WCET bounds. In the future we will explore to use multiple Patmos cores in the T-CREST multicore platform [28], [29] to speedup the network stack and the application using the network stack.…”

Section: Prototype Implementationmentioning

confidence: 99%

tpIP: A Time-Predictable TCP/IP Stack for Cyber-Physical Systems

Schoeberl

Pedersen

2018

2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)

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Cyber-physical systems are networks of computers connected to the physical world. Often the interaction with the physical world is time critical. In that case computation and communication must be performed in real time. However, a standard implementation of a network stack is hardly time predictable.This paper addresses the challenge of real-time communication for time-critical cyber-physical systems with a time-predictable network stack. We present tpIP, a real-time implementation of the TCP/IP stack. We achieve time predictability by two properties:(1) the application interface is based on polling functions, instead of blocking sockets, that fits for periodic real-time tasks; (2) the implementation is carefully crafted to enable static worst-case execution time analysis of all functions.

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“…The T-CREST multicore is a processor optimized for low WCET and to simplify static WCET analysis [15], [16]. All components have been designed to be time-predictable and to enable WCET analysis.…”

Section: The T-crest Platformmentioning

confidence: 99%

Hardlock: A Concurrent Real-Time Multicore Locking Unit

Strøm

Schoeberl

2018

2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)

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To use multicore processors, an application needs to split computation into several threads that execute on different processing cores. As those threads work together towards a common goal, they need to exchange data in a controlled way. A common communication paradigm between cooperating threads is using shared data structures protected by locks. Implementing a lock on top of shared memory can easily result in a bottleneck on a multicore processor due to the congestion on the shared memory. However, the number of locks in use is usually low and using the large external memory to support locks is over-provisioning a resource. This paper presents an efficient implementation of locking by providing dedicated hardware support for locking on-chip. This locking unit supports a restricted number of locks without the need to get off-chip. The unit can process lock acquisitions in 2 clock cycles and releases in 1 clock cycle.

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A Multicore Processor for Time-Critical Applications

Cited by 14 publications

References 11 publications

A Time-predictable TTEthenet Node

A Time-predictable TTEthenet Node

tpIP: A Time-Predictable TCP/IP Stack for Cyber-Physical Systems

Hardlock: A Concurrent Real-Time Multicore Locking Unit

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