A Multicast Tree Router for Multichip Neuromorphic Systems

Abstract

Abstract-We present a tree router for multichip systems that guarantees deadlock-free multicast packet routing without dropping packets or restricting their length. Multicast routing is required to efficiently connect massively parallel systems' computational units when each unit is connected to thousands of others residing on multiple chips, which is the case in neuromorphic systems. Our tree router implements this one-tomany routing by branching recursively-broadcasting the packet within a specified subtree. Within this subtree, the packet is only accepted by chips that have been programmed to do so. This approach boosts throughput because memory look-ups are avoided enroute, and keeps the header compact because it only specifies the route to the subtree's root. Deadlock is avoided by routing in two phases-an upward phase and a downward phase-and by restricting branching to the downward phase. This design is the first fully implemented wormhole router with packet-branching that can never deadlock. The design's effectiveness is demonstrated in Neurogrid, a million-neuron neuromorphic system consisting of sixteen chips. Each chip has a 256×256 silicon-neuron array integrated with a full-custom asynchronous VLSI implementation of the router that delivers up to 1.17G words/s across the sixteen-chip network with less than 1µs jitter.

Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems

“…Many years have passed since the first publication on neuromorphic electronic systems [11], and remarkable progress has been made by the small but vibrant Neuromorphic Engineering (NE) community [162], [163]. For example the NE community has mastered the art of building real-time sensory-motor reactive systems, by interfacing circuits and networks of the type described in this paper with neuromorphic event-based sensors [164]; new promising neural-based approaches have been proposed that link neuromorphic systems to machine learning [165]- [169]; substantial progress has been made in the field of neuromorphic robots [170]; and we are now able to engineer both large scale neuromorphic systems (e.g., that comprise of the order of 10 6 neurons [171]) and complex multi-chip neuromorphic systems (e.g., that can exhibit cognitive abilities [20]). However, compared to the progress made in more conventional standard engineering and technology fields, the rate of progress in NE might appear to be disappointingly small.…”

A path towards average-case silicon via asynchronous resilient bundled-data design

“…For example, Intel showed that highperformance quasi-delay-insensitive (QDI) design is sufficiently robust and effective for high performance networking chips [17]. Moreover, the challenges of managing a global clock in large neuromorphic chips, have driven IBM [18] and Stanford [19] to adopt an asynchronous mostly QDI interconnect. Other academic researchers have found that built-in flowcontrol in bundled-data network-on-chips lead to significant benefits in terms of latency and area compared to synchronous counterparts [15].…”

Impresjony słów. Język naturalnych i sztucznych sieci neuronowych

“…Zbieżność tej koncepcji z architekturą mózgu naturalnego stwarza możliwość zbudowania sztucznego systemu zdolnego do świadomego działania, a jego grafowa struktura dostosowana do równoległego przetwarzania informacji wzbudza nadzieję na możliwość szybkiej realizacji technicznej takiego przedsięwzięcia. Tym bardziej, że technologia dostarcza podzespołów doskonale nadających się do roli elektronicznego podłoża do zdefiniowanych w modelu Horzyka funkcji [Benjamin i in., 2014;Merolla i in., 2014]. Zaproponowany model sieci neuronowej posiada dostateczną elastyczność, aby uzupełnić go o funkcje niezbędne do tak sformułowanego zadania.…”