A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels

Sengupta, Anirban; Sedaghat, Reza; Sarkar, Pallabi

doi:10.1016/j.swevo.2012.06.003

Cited by 31 publications

(7 citation statements)

References 16 publications

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“…The authors remark on six main multi-objective methods applied for HLS DSE: evolutionary algorithms, single-solution-based heuristics, problem-specific heuristics, branch-and-X, learning-based methods, and swarm intelligence systems. Some examples are the studies presented in [64], [65], [66], [67], [68], [69], [70], [71], [72], and [73].…”

Section: B Design Space Exploration and Metricsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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Section: B Design Space Exploration and Metricsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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“…The temporal binding (scheduling) is often removed from the scope since it dramatically increases the design space. Nevertheless, some research has been conducted around scheduling and allocation in various environments [2,3,17,26,27,28]. In 2022, Wan and Zeng [35] proposed a novel but highly limited co-design methodology specialized for modular CPS within a production setting.…”

Section: Related Workmentioning

confidence: 99%

Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions

Herget

Saadatmand

Bor

et al. 2022

2022 25th Euromicro Conference on Digital System Design (DSD)

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Industrial Cyber-Physical Systems (CPS) are complex heterogeneous and distributed computing systems, typically integrating and interconnecting a large number of subsystems and containing a substantial number of hardware and software components. Producers of these distributed Cyber-Physical Systems (dCPS) face serious challenges with respect to designing the next generations of these machines and require proper support in making (early) design decisions to avoid expensive and time consuming oversights. This calls for efficient and scalable systemlevel Design Space Exploration (DSE) methods for dCPS.In this position paper, we review the current state of the art in DSE, and argue that efficient and scalable DSE technology for dCPS is more or less non-existing and constitutes a largely unchartered research area. Moreover, we identify several research challenges that need to be addressed and discuss possible directions for targeting such DSE technology for dCPS.

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“…The algorithm stops when an end condition is satisfied. Crossover takes two individuals and uses random point(s) to cut the chromosome in two segments, a 'head' and 'tail' segment [39,40,41]. The tail segments are swapped over to produce two new chromosomes.…”

Section: Genetic Algorithmsmentioning

confidence: 99%

A Delta diagram synthesis for IoT optimization with grey wolf driven multi-objective automation

Siddavaatam¹

2021

Preprint

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Today, Internet of Things (IoT) is a major paradigm shift that will mark an epoch in communication technology such that every physical object can be connected to the Internet. With the advent of 5G communications, IoT is in urgent need of optimized architectures that can efficiently support wide ranging heterogeneous multi-objective requirements of communication, hardware and security aspects. The optimization challenges are rooted in the technology and how the information is acquired and manipulated by this technology. My research in this thesis provides a description of compelling challenges faced by IoT and how to mitigate these challenges by designing resource-aware communication protocols, resource- constrained device hardware with low computing power and low-powered computational security enhancements. This thesis lays the foundation for optimizing these challenging IoT paradigms by introducing a novel Delta-Diagram based synthesizing model. The Delta- Diagram provides a road-map linking the behavioral and structural domains of a given IoT paradigm to generate respective optimizer domain parameters, which can be utilized by any optimizer framework. The fundamental part of the communication synthesizer is a mathematical model, developed to obtain the best possible routing paths and communication parameters among things. The ultimate aim of the entire synthesis process is to devise a design automation tool for IoT, which exploits the interrelations between different layer functionalities. This thesis also proposes a novel cross-layer Grey wolf optimizer for IoT, which outperforms some of the contemporary optimizer algorithms such as Particle Swarm, Genetic Algorithm, Differential Evolution optimizers in solving unimodal, multi-modal and composition benchmark problems. The purpose of this optimizer is to accurately capture both the high heterogeneity of the IoT and the impact of the Internet as part of delta diagram synthesis enabled network architecture. In addition, the Grey wolf optimizer for IoT plays a crucial role in design exploration of system on chip architecture for IoT device hardware. The results generated by the optimizer yielded the most optimum feasible solutions in the design space exploration process of the IoT.

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A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels

Cited by 31 publications

References 16 publications

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions

A Delta diagram synthesis for IoT optimization with grey wolf driven multi-objective automation

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