A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS

Yokoyama-Martin, D.A.; Kant, Krishna; Stonick, J.T.; Caffee, A.; Gamble, E. Kolet; Jones, Curtis G.; McNeal, Jeff D.; Parker, James F.; Segelken, R.; Sonntag, J.; Umino, K.; Upton, J.; Weinlader, D.; Wolfer, S.

doi:10.1109/cicc.2006.320970

Cited by 6 publications

(7 citation statements)

References 3 publications

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“…Therefore, I 1 and I 2 are related by (2). The specific values of I 1 and I 2 are dependent on the currents of each device in the differential pairs which are dependent on the input and reference signals at their gates according to (3).…”

Section: Comparatormentioning

confidence: 99%

“…In this design, the differential signal level is compared to a differential reference, unlike many previous systems [2] [3]. A novel continuous-time comparator topology is presented in section III that is capable of comparing differential signals.…”

Section: Los Detector Architecturementioning

confidence: 99%

“…As new communications applications are expanding, demands for wired serial communication is continuously increasing, and many advancements and new designs of transceivers are seen in the literature that can support multiple standards and protocols including SATA, PCI Express (PCIe), XAUI, LVDS, Interlaken and Infiniband protocols [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

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A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

Kawar

Abugharbieh

Al-Akel

et al. 2014

2014 IEEE International Conference on IC Design &Amp; Technology

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This paper presents a 10 Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS and is capable of operating with a 29.5mV internal eye opening and a 67mV external eye opening at the input pads. It consumes 69uW from a 0.9V supply at 10 Gbps and properly asserts an LOS state in 6.8 nsec. A novel comparator topology, which is a part of the LOS circuit, is also presented. It compares a differential input to a differential reference voltage. Design and layout were implemented using Synopsys Custom Designer with 28nm CMOS device models. The LOS detector can reduce power consumption and bit error rate (BER) of serial transceivers.

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Section: Comparatormentioning

confidence: 99%

Section: Los Detector Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

Kawar

Abugharbieh

Al-Akel

et al. 2014

2014 IEEE International Conference on IC Design &Amp; Technology

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show abstract

“…To enable work with multiple standards, several multi-standard transceivers have been reported [3][4][5]. A 1.5-3.125 Gb/s serial transceiver was demonstrated in [3], which supported PCIe, SATA, and XAUI in 90nm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

Hou

Yang

Liu

et al. 2014

Sci. China Inf. Sci.

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A power-efficient and low-cost 1.0625-3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel (FC), Peripheral Component Interconnect Express (PCIe), and RapidIO applications. To support multiple standards with a single low power and low cost design, the transceiver presented here uses a wide swing range source-series-terminated (SST) transmitter (TX), a passive receiver (RX) equalizer, a dual-loop phase locked loop (PLL) and a mixed signal clock and data recovery (CDR) unit. The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver. The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR's reference. A CDR with a phase interpolator (PI) is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm. The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm 2. With supply voltages of 1.2 V and 3.3 V, the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at 3.125 Gb/s.

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“…For the same voltage swing, the power consumption of a current-mode driver, however, is larger than that of a voltage-mode driver and therefore a voltage-mode driver is drawing lots of interest especially for low-power serial link [2,3].…”

Section: Introductionmentioning

confidence: 99%

A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

Bae¹,

Choi²,

Ahn³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

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A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS

Cited by 6 publications

References 3 publications

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

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