A multi-processor NoC-based architecture for real-time image/video enhancement

Saponara, Sergio; Fanucci, Luca; Petri, Esa

doi:10.1007/s11554-011-0215-8

Cited by 23 publications

(11 citation statements)

References 36 publications

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“…The irregular data flow and the scheduling due to the nature of image enhancement algorithms affected both computing and communication infrastructures. Saponara et al [13] presented the multiprocessor architecture for low-power image and video enhancement applications based on following paradigms: array of multiple heterogeneous tiles and the utilization of network-on-chip (NoC) to alleviate the bottleneck problem in classic circuit-switched bus architectures. The integrated techniques that covered the filtering and motion analysis were offered poor performance in the bounded complexity budget.…”

Section: Related Workmentioning

confidence: 99%

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

Jayavathi¹,

Shenbagavalli²

2017

J Real-Time Image Proc

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Embedded Block Coding with Optimized Truncation (EBCOT) used in JPEG2000 standard performs the sequential processing of code blocks for clear images. The employment of Matrix Quantizer (MQ) in EBCOT reduces the computational burden by generating the context decision pair from probabilistic estimation. But, it consumes huge devices and occupies large memory space that leads to the difficulties in hardware design. The bit truncation in MQ-coder reduces the computational complexities that lead to a reduction in the memory space occupation in the hardware platform. This paper proposes the Auxiliary Minutest MQ (AMMQ) architecture for bit truncation in the probability estimation of context decision pair making. The reduction in a number of bits minimizes the slice registers and lookup tables utilization that offers less flipflop consumption to achieve the compact chip development for JPEG2000 compression. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The comparative analysis of proposed AMMQ-coder architecture with the existing architectures regarding the memory assures the effectiveness of new way of bit truncation scheme in the JPEG2000 compression.

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Section: Related Workmentioning

confidence: 99%

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

Jayavathi¹,

Shenbagavalli²

2017

J Real-Time Image Proc

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“…Although some research results related to the memory and communication architectures can be found in the literature [28,30,14,17,23] in the context of programmable on-chip multiprocessor systems, the communication architectures were proposed there for the much larger and much slower programmable processors. They are not adequate for the small and ultra-fast hardware processors of the massively-parallel multi-processor accelerators, due to a much too low bandwidth and scalability issues.…”

Section: Related Researchmentioning

confidence: 99%

Scalable communication architectures for massively parallel hardware multi-processors

Jan

Jówiak

2012

Journal of Parallel and Distributed Computing

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“…Although some research results related to the memory and communication architectures can be found in the literature [15][16][17][18][19][20][21] in the context of programmable on-chip multiprocessor systems, the memory and communication architectures were proposed there for the much larger and much slower programmable processors. They are not adequate for the small and ultra-fast hardware processors of the massively parallel multi-processor accelerators, due to a much too low bandwidth and scalability issues.…”

Section: Issues and Requirements Of Communication And Memory Architecmentioning

confidence: 99%

Communication and Memory Architecture Design of Application‐Specific High‐End Multiprocessors

Jan

Jóźwiak

2012

VLSI Design

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This paper is devoted to the design of communication and memory architectures of massively parallel hardware multiprocessors necessary for the implementation of highly demanding applications. We demonstrated that for the massively parallel hardware multiprocessors the traditionally used flat communication architectures and multi-port memories do not scale well, and the memory and communication network influence on both the throughput and circuit area dominates the processors influence. To resolve the problems and ensure scalability, we proposed to design highly optimized application-specific hierarchical and/or partitioned communication and memory architectures through exploring and exploiting the regularity and hierarchy of the actual data flows of a given application. Furthermore, we proposed some data distribution and related data mapping schemes in the shared (global) partitioned memories with the aim to eliminate the memory access conflicts, as well as, to ensure that our communication design strategies will be applicable. We incorporated these architecture synthesis strategies into our quality-driven model-based multi-processor design method and related automated architecture exploration framework. Using this framework, we performed a large series of experiments that demonstrate many various important features of the synthesized memory and communication architectures. They also demonstrate that our method and related framework are able to efficiently synthesize well scalable memory and communication architectures even for the high-end multiprocessors. The gains as high as 12-times in performance and 25-times in area can be obtained when using the hierarchical communication networks instead of the flat networks. However, for the high parallelism levels only the partitioned approach ensures the scalability in performance.

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A multi-processor NoC-based architecture for real-time image/video enhancement

Cited by 23 publications

References 36 publications

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

Scalable communication architectures for massively parallel hardware multi-processors

Communication and Memory Architecture Design of Application‐Specific High‐End Multiprocessors

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