A Multi-Output Multi-String High-Efficiency WLED Driver Using 40 nm CMOS Technology

Abstract

In this work, a multi-independent-output, multi-string, high-efficiency, boost-converter-based white LED (WLED) driver architecture is proposed. It utilizes a single inductor main switch with a common maximum duty cycle controller (MDCC) in the feedback loop. A simple pulse skipping controller (PSC) is utilized in each high-side switch of the multiple independent outputs. Despite the presence of multiple independent outputs, a single over-voltage protection (OVP) circuit is used at the output to protect the circuit from any voltage above 27 V. An open circuit in any of the strings is addressed, in addition to the LED’s short-circuit conditions. Excellent current matching between strings is achieved, despite the low ON-resistance (Rdson) of transistors used in the 40 nm process. Most circuits are designed in digital CMOS logic to overcome the extreme process variations in the 40 nm node. Compared to a single output parallel strings topology, a 50% improvement in efficiency is achieved relative to extremely unbalanced strings. Three strings are used in this proposal, but more strings can be supported with the same topology. Each string is driven by a 25 mA current sink. An input voltage of 3.2–4.2 V and an output voltage up to 27 V are supported.

Design Aspects of a Single-Output Multi-String WLED Driver Using 40 nm CMOS Technology

“…Different topologies are employed for current sinks, such as single-transistor or Cascode current mirror [4]. The single-transistor current mirror suffers from low output impedance, making it less accurate as a current sink for WLED driver applications.…”

“…As a result, customized WLED drivers are necessary. When it comes to designing a WLEDs driver, there are different architectures to consider, including boost-based [4,5], buck-based [6,7], and charge pump-based WLED drivers [8], as well as many others [9][10][11]. Boost-based architectures are preferable for smartphone applications, as the available input voltage, i.e., the battery voltage (3.2-4.2 V), is well below the required output voltage (20-40 V).…”

A Design Methodology of High-Efficiency Dimmable Current Sink for Current-Regulated Drivers

“…The chosen design specifications are listed in Table 2. This data is based on the work presented in [8,19]. The TSMC 40 nm CMOS technology is utilized in the ADS CAD tool to implement and simulate the design.…”

“…Moreover, lower node processes yield both lower area and power loss. However, designing a current sink driver using a lower node process is challenging due to the lower output impedance of the MOS device, i.e., r o [7,8]. Due to the popularity of the current sink, a systematic, scalable and easy-to-follow design methodology is needed [9][10][11][12][13][14].…”