A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS

Palumbo, G.; Scotti, Giuseppe

doi:10.1109/tcsi.2020.3008487

Cited by 8 publications

(3 citation statements)

References 33 publications

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“…The realized design is a high-speed, low-voltage power and high-efficiency static frequency divider (FMCML) method based on the folded MOS current mode logic. A modeling strategy was introduced to analyze the propagation delay and the power consumption dependence in the bias current of cell division by 2 (DIV2) [1,2]. A new current model of CMOS technology using a trans-linear RMS-DC converter has been introduced.…”

Section: Literature Surveymentioning

confidence: 99%

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Pradeep¹,

Rani²,

Kumar³

et al. 2021

Wireless Pers Commun

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MOS current mode logic (MCML) is one of the most promising logic functions to counteract power analysis attacks. The static power MCML standard cells are significantly higher than the static CMOS logic to achieve an equivalent function. As a result, using such logical patterns is very limited in portable devices. The strange thing is that these devices are the most sensitive to physical attacks, which will benefit more people from passing MCML. The propose to overcome this limitation by significantly reducing the static power consumption of MCML-based full adder circuits. For this reason, current control by adaptive (ACCT) -MCML standard cell library is provided in each transistor cell suspension. The effect of sleep transistors on performance and area is negligible. In addition, the proposed difference library is compatible with Micro wind tools. The integrated real-time digital signal processing application, where the drive current must be high. The conventional design will have a low-efficiency supply voltage with low capacitance; even when operating, the circuit speed will be faster, and the delay will be high. So the proposed 14 T full adder based integrated circuit and adder are based on ACCT, which High power consumption, which has become an essential standard operation for the design of energy-efficient dedicated circuits, has become the primary function and compact device design, possible output. The coefficient plays a significant role in planning energy-saving processors and determining processor performance. Especially, the switching behavior is to diminish the power consumption of the design MCML full ladder logic. However, the performance of the circuit is less than the full adder binary logic. The proposed circuit's correctness and effectiveness are verified by Micro wind with a proposed MCML process of 0.13 μm and a power supply voltage of 4.2 V.

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Section: Literature Surveymentioning

confidence: 99%

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Pradeep¹,

Rani²,

Kumar³

et al. 2021

Wireless Pers Commun

View full text Add to dashboard Cite

show abstract

“…Since the late 1990s and up to recent years, several digital gate models have been developed based on the small-signal representation of the transistor with an improved modeling of its parasitic capacitors, suitable for large signal swings. Such models covered both CML [10][11][12] and MCML gates [13][14][15][16]; they were proficiently used to optimize the design of standard CML and MCML gates [17][18][19][20], and, recently, were also used for advanced gates developed for very low-voltage environments [21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Simple and Accurate Model for the Propagation Delay in MCML Gates

2023

Self Cite

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In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively.

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“…In particular, the approach named multiple-tail current mode logic (MTCML) [31] provides a shallow depth (based on a different kind of folding with respect to the one used in the FMCML of [30]) and could halve the number of stacked stages, or even further reduce it, but for gate fan-in higher than three it cannot in general achieve a minimum supply voltage as low as the one of a MCML inverter. On the other hand, the novel multi-folded MCML, which generalizes the strategy of the FMCML, regardless of the gate fan-in, is able to work with a minimum supply voltage as low as the one of a MCML inverter [32].…”

Section: Introductionmentioning

confidence: 99%

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

2021

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Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

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A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS

Cited by 8 publications

References 33 publications

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Simple and Accurate Model for the Propagation Delay in MCML Gates

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

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