A Multi-channel Real Time Implementation of Dual Tree Complex Wavelet Transform in Field Programmable Gate Arrays

Canbay, Ferhat; Levent, Vecdi Emre; Serbes, Görkem; Uğurdağ, H. Fatih; Gören, Sezer; Aydin, Nizamettin

doi:10.1007/978-3-319-32703-7_24

Cited by 3 publications

(2 citation statements)

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“…The proposed code generator can generate the optimum architecture for all our four approaches. The results of multi‐channel approach [16] can be seen in Table 1. Code generator is used with word sizes of 12, 18, and 32 bits.…”

Section: Resultsmentioning

confidence: 99%

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Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications

Canbay

Levent

Serbes³

et al. 2016

Healthcare Technology Letters

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The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed. . However, in FT the time information is lost, and therefore it shows limited performance while processing non-stationary parts of BSs. Short time FT (STFT) is employed as a solution for the lack of time-information drawback of FT in various studies [2] by shifting a window onto the time axis and applying FT only to the signal component beneath this window, whereas, in the STFT, analysis window has fixed length for the entire time-axis resulting in a fixed time-frequency resolution. Continuous wavelet transform (WT) is frequently used in order to attain an adaptive time-frequency resolution by using wavelets with varying sizes; low frequencies are analysed over wide time wavelets, and high frequencies over narrow time wavelets. However, the complex WT (CWT) is computationally expensive and produces a vast amount of data at the end of analysis. Therefore, in real-time applications, in order to reduce memory requirements and to increase the computation speed of the analysis, discrete WT (DWT), in which the scale and translation parameters are discretised, is commonly employed [3]. Previously, DWT was used in the pre-processing, de-noising, and feature extraction steps of BSs analysis [4]. However, the DWT suffers from being shift-invariant and this results in corruptive sensitivity to the phase-shifts occurring in the input signal. As an example, when the DWT is used as a de-noising operator for embolic signals in [5], the distorted coefficients obtained with the DWT decreases the performance. Dual tree CWT (DTCWT), which is an improved version of the DWT with limited redundancy, is proposed in [6] to overcome the lack of shift-invariance property of the classical DWT. The DTCWT consists of two separate discret...

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Section: Resultsmentioning

confidence: 99%

“…In the third implementation, to improve the area efficiency one step further, an adder and a multiplier are used for all channels. The details of these three implementations can be seen in our previous studies [14][15][16].…”

Section: Verilog Implementation and Proposed Code Generatormentioning

confidence: 99%