A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration

A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

“…Therefore, the output count should equal 0.15% of the TDC input samples. Consequently, if the counter is reset every 2000 reference cycles the expected output count should be 3 on average as illustrated by (12). This reference count of 3 is deducted from the output count using a subtractor; moreover, this error signal is sampled by an accumulator at a rate of F ref /2000.…”

“…In addition, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the resolution control loop of [8]. Furthermore, the proposed resolution control loop has a lower settling time compared to that of the resolution control loop of [12] and can operate simultaneously with a loop-gain control loop.…”

“…However, the TDC resolution obtained by the analysis in [11] does not guarantee the linearity of the TDC transfer function across the range of the TDC input time error. Furthermore, another alternative resolution control loop based on jitter monitoring has been proposed in [12]. This resolution control loop monitors the distribution of the TDC input time error and alters the TDC resolution until a local minimum of σ ∆t is achieved rather than targeting a specific time resolution.…”

“…However, a large number of observation cycles is needed to generate an accurate distribution of the TDC input time error to minimize the probability of wrong decisions [13]. Consequently, the resolution control loop in [12] requires a large settling time. Moreover, it cannot operate simultaneously with a loop-gain control loop because only one ADPLL parameter can be varied at a time.…”