A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

Abstract

Today's electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS'89 benchmark circuits.

Test Data Compression Using Variable Prefix Run Length (VPRL) Code

“…Table 4 and Figure 3 projects the Comparison of Compression ratios of proposed method with other test independent Compression techniques, such as the Golomb [3], FDR [4], ALT-FDR [14], EFDR [5], AVR [2], MAVR [22]. It shows that proposed method yields the best Compression ratio compared to other codes.…”

“…There are many techniques to control the volume of test data, test application time and power consumption in test mode. Test data volume and power reduction can be achieved by utilizing Built-in-Self-test (BIST) [2,3], test data compaction or test data compression techniques [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][20][21][22]. However, BIST requires a longer test application time.…”