A modified Genetic Algorithm approach to minimize total weighted tardiness with stochastic rework and reprocessing times

Raghavan, Venkatesh Arasanipalai; Yoon, Sang Won; Srihari, K.

doi:10.1016/j.cie.2018.06.002

Cited by 9 publications

(1 citation statement)

References 33 publications

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“…Besides the rule-based methods, some studies investigating meta-heuristics have been conducted to improve their particular objectives through exhaustive search over solution spaces [2,3,[28][29][30]. However, they require considerably long computation time to reach optimality, which leads to difficulties in applying them to a real-world assembly line.…”

Section: Introductionmentioning

confidence: 99%

Learning to Dispatch Operations with Intentional Delay for Re-Entrant Multiple-Chip Product Assembly Lines

et al. 2018

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As the demand for small devices with embedded flash memory increases, semiconductor manufacturers have been recently focusing on producing high-capacity multiple-chip products (MCPs). Due to the frequently re-entrant lots between the die attach (DA) and wire bonding (WB) assembly stages in MCP production, increased flow time and decreased resource utilization are unavoidable. In this paper, we propose a dispatcher based on artificial neural networks, which minimizes the flow time while maintaining high utilization of resources at the same time through exploiting the possible intentional delays on DA stage. Specifically, the proposed dispatcher learns the assignment preferences between available lots and DA resources based on assembly line data generated by using a simulator, then the proposed dispatcher performs lot dispatching decisions by considering the intentional delays. The numerical experiments were performed under various configurations of the MCP assembly lines, and the results show that the proposed dispatcher outperformed the existing methods.

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