A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories

Knödtel, Johannes; Fritscher, Markus; Reiser, Daniel; Fey, Dietmar; Breiling, Marco; Reichenbach, Marc

doi:10.1109/mocast49295.2020.9200241

Cited by 4 publications

(2 citation statements)

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“…For the concept of the embedded memory block, a ternary memory cell was considered to store ternary weights for the ANN application [17,18], more specifically one highly resistive state (HRS) and two low-resistive states (LRS1 and LRS2), but it is not limited to just three states and can be expanded to further multi-level operation. The ternary application results in four different operations: Switching directly between LRS1 and LRS2 is not intended in this technology due to stability reasons [19].…”

Section: Concept Overviewmentioning

confidence: 99%

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

et al. 2021

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Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the individual neurons. This paper introduces a memory block using resistive memory cells (RRAM) to realize this weight and bias storage in an embedded and distributed way while also offering programming and multi-level ability. By implementing power gating, overall power consumption is decreased significantly without data loss by taking advantage of the non-volatility of the RRAM technology. Due to the versatility of the peripheral circuitry, the presented memory concept can be adapted to different applications and RRAM technologies.

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Section: Concept Overviewmentioning

confidence: 99%

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

et al. 2021

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“…Therefore, weights and matrix multiplications of a neural network can be stored inside one ReRAM cell, and a neural network can be implemented by saving all network weights directly on the chip (Perez et al, 2020 ). As a result, external memory access is avoided, which can lower the energy consumption drastically (Knödtel et al, 2020 ). The high-density integration on the chip allows for the ReRAM cells to be closely attached to digital computation units, which decreases energy consumption by avoiding long data paths on the chip.…”

Section: Interface With the Embedded Computer Architecturementioning

confidence: 99%

Adaptation Strategies for Personalized Gait Neuroprosthetics

et al. 2021

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Personalization of gait neuroprosthetics is paramount to ensure their efficacy for users, who experience severe limitations in mobility without an assistive device. Our goal is to develop assistive devices that collaborate with and are tailored to their users, while allowing them to use as much of their existing capabilities as possible. Currently, personalization of devices is challenging, and technological advances are required to achieve this goal. Therefore, this paper presents an overview of challenges and research directions regarding an interface with the peripheral nervous system, an interface with the central nervous system, and the requirements of interface computing architectures. The interface should be modular and adaptable, such that it can provide assistance where it is needed. Novel data processing technology should be developed to allow for real-time processing while accounting for signal variations in the human. Personalized biomechanical models and simulation techniques should be developed to predict assisted walking motions and interactions between the user and the device. Furthermore, the advantages of interfacing with both the brain and the spinal cord or the periphery should be further explored. Technological advances of interface computing architecture should focus on learning on the chip to achieve further personalization. Furthermore, energy consumption should be low to allow for longer use of the neuroprosthesis. In-memory processing combined with resistive random access memory is a promising technology for both. This paper discusses the aforementioned aspects to highlight new directions for future research in gait neuroprosthetics.

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Wind speed multistep forecasting model using a hybrid decomposition technique and a selfish herd optimizer-based deep neural network

Vidya

Janani

2021

Soft Comput

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A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories

Cited by 4 publications

References 18 publications

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

Adaptation Strategies for Personalized Gait Neuroprosthetics

Wind speed multistep forecasting model using a hybrid decomposition technique and a selfish herd optimizer-based deep neural network

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