A Miniature Real-Time Re-Configurable Radar Waveform Synthesizer for Uav Based Radar

Abstract

Abstract-Radar waveform synthesizer is a key component in radar system as it determines the best achievable resolution. In this paper, a miniature and low cost radar waveform synthesizer is proposed. The synthesizer is targeted for Unmanned Aerial Vehicle (UAV) based radar system applications that require miniaturized equipment due to limited space in aircraft's fuselage. The waveform synthesizer has been developed using Altera DE3 development board (Stratix III FPGA) and a custom made dual-channel 420 MSPS HS-DAC board. The proposed system is capable of generating various types of radar waveforms: a) Linear Frequency Modulated (LFM) or chirp pulse, b) Frequency Modulated Continuous Wave (FMCW), and c) Calibration Tone (Cal-Tone), for use in different types of radar applications. The distinguishing feature of the proposed synthesizer is its capability in re-configuring the signal properties in real-time. The performance of the synthesizer has been benchmarked with commercially available radar waveform synthesizer and comparable performance has been observed.

An FPGA based Real-Time Multi-Target Synthetic Aperture Radar Echoes Synthesizer

“…Recently, DDS has been widely used in radar waveform synthesis due to its flexibility in radar waveform re-configuration without the needs of hardware reconfiguration. Detailed operating principle of a DDS waveform generator for SAR system can be found in [6,17].…”

“…However, a modern radar system, with the present of massive on-board processing hardware resources, can process the collected data in real-time during the flight mission. Most seen computing platform used is either digital signal processors (DSP) or field programmable gate array (FPGA) [6,7], or both [8]. DSP exhibits the advantages in simplicity of usage while FPGA has clear superiority ability in parallel processing.…”

FPGA-based I/Q chirp generator using first quadrant DDS compression for pulse compression radar

“…This design needs higher speed ROM during operation because of the sequential demultiplexing requirement for selecting In Phase and Quadrature part element. M. Y. Chua et al, presenting memory reduction technique using only first quadrant SINE saved into memory, this technique will save 75% of memory space requirement [5]. R. K. Sharma and Gargi Upadhyaya reduced memory size using phase truncation and quadrature sine symmetry [6].…”