A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect

Lin, Yong-Yu; Chen, Fan-Ta; Chen, Wei-Zen

doi:10.1109/vlsi-dat49148.2020.9196262

Cited by 3 publications

(1 citation statement)

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“…With the wide bandwidth nature, the unlicensed 60 GHz band is considered as a solution for the several short distance and high data rate applications, such as wireless backhaul, augmented reality (AR), and virtual reality (VR). Benefiting from the aggressive scaling down of a CMOS transistor, several 60 GHz transceivers for wireless communication and radar sensing have been realized [1][2][3][4][5]. For above applications, the higher order modulation scheme, e.g., 16QAM, is required to achieve the high throughput rate.…”

Section: Introductionmentioning

confidence: 99%

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Niu

et al. 2022

Electronics

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This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

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