A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive Validation

Abstract

This article presents a wideband series-Doherty power amplifier (SDPA) for millimeter-wave (mm-wave) fifthgeneration (5G) applications. It features a compact two-step impedance inverting-based series-Doherty power combiner that provides broadband close-to-perfect power back-off (PBO) efficiency enhancement. The amplitude-to-amplitude (AM-AM)/amplitude-to-phase (AM-PM) performance of the load-modulated Doherty power amplifier for broadband operation is analyzed. We also devise a post-silicon inter-stage passive validation (PSIV) approach to evaluate the mm-wave chip prototype utilizing the embedded voltage root mean square detectors. The proposed SDPA is realized in a 40-nm bulk CMOS, and it delivers 20.4 dBm P SAT with 39.1%/34% PAE at 0-/6-dB PBO. Over a 23.5-30 GHz band, its PAE is >24% at 6-dB PBO. At 27 GHz, applying a "2 GHz 16-quadratic-amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM)" signal, the proposed SDPA generates 10.2 dBm average power with 18.9% average PAE. The average error vector magnitude is better than −24.5 dB without digital predistortion for a "400-MHz 64-QAM OFDM" signal while generating an average output power of 8.8 dBm with 15% PAE. The AM-AM/AM-PM of the realized SDPA is investigated by employing a "50-MHz 64-QAM OFDM" signal, validating our analysis and showing that the linearity limitation of DPAs is systematic and predictable. Utilizing the proposed PSIV approach, the frequency response of the input/inter-stage passive circuits is measured, indicating an excellent agreement with 3-D electromagnetic (EM) simulation results.

A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

“…Some important conclusions can be drawn from (7) and (8). First, with given values of α and R opt,M , the load modulation behavior of the proposed Doherty topology can be determined.…”

“…First, the ITR between N × R opt and 50 Ω is substantially lower than that of the parallel topology when R opt is small [9]. Second, the elimination of the λ/4 TL after the Main PA enhances both the bandwidth and the linearity [8]. Nonetheless, while the series DPA topology has been successfully implemented in CMOS processes [8][9][10][11][12][13][14], its application in printed circuit board (PCB) or monolithic microwave integrated circuit (MMIC) processes is still rarely reported.…”

“…The Doherty power amplifier (DPA) is the most widely used architecture for improving the OBO efficiency of PAs due to its intrinsic linearity and low baseband overhead [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]. A DPA typically comprises a Main PA and an Auxiliary PA, with its OBO efficiency enhanced through active load modulation between these two sub-PAs.…”

“…DPA comprises two fundamental topologies: parallel and series, as depicted in Figure 1 [8]. In the parallel topology, the Main PA is connected in parallel with the Auxiliary PA via a λ/4 transmission line (TL), resulting in a load impedance of R opt /2.…”

“…Second, the elimination of the λ/4 TL after the Main PA enhances both the bandwidth and the linearity [8]. Nonetheless, while the series DPA topology has been successfully implemented in CMOS processes [8][9][10][11][12][13][14], its application in printed circuit board (PCB) or monolithic microwave integrated circuit (MMIC) processes is still rarely reported. This is primarily attributed to the constraints of these processes, which generally contain only two or three metal layers (including the ground layer), posing significant challenges in the fabrication of transformers with high coupling factors.…”