2010 IEEE International Solid-State Circuits Conference - (ISSCC) 2010
DOI: 10.1109/isscc.2010.5433998
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A microcontroller-based PVT control system for a 65nm 72Mb synchronous SRAM

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Cited by 3 publications
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“…The authors in [73] proposed a data randomization scheme for a subthreshold SRAM to reduce bitline swing degradation against PVT variations. In [74], the authors present a digital controller with static body-bias control generation schemes for an SRAM array and peripherals to optimize the leakage and improve the performance. This work addresses PVT variation challenges by dynamically controlling three design parameters using a ring oscillator (RO) based process corner and V DD droop detection: 1) body-biasing, 2) adaptive peripheral assist technique selection for an SRAM, and 3) droop detection and mitigation.…”
Section: The Effect Of Soft-errors In Subthreshold Sram Designmentioning
confidence: 99%
“…The authors in [73] proposed a data randomization scheme for a subthreshold SRAM to reduce bitline swing degradation against PVT variations. In [74], the authors present a digital controller with static body-bias control generation schemes for an SRAM array and peripherals to optimize the leakage and improve the performance. This work addresses PVT variation challenges by dynamically controlling three design parameters using a ring oscillator (RO) based process corner and V DD droop detection: 1) body-biasing, 2) adaptive peripheral assist technique selection for an SRAM, and 3) droop detection and mitigation.…”
Section: The Effect Of Soft-errors In Subthreshold Sram Designmentioning
confidence: 99%