A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

Abstract

International audienceIt is well-known that today׳s compilers and state of the art libraries have three major drawbacks. First, the compiler sub-problems are optimized separately; this is not efficient because the separate sub-problems optimization gives a different schedule for each sub-problem and these schedules cannot coexist as the refining of one, causes the degradation of another. Second, they take into account only part of the specific algorithm׳s information. Third, they take into account only a few hardware architecture parameters. These approaches cannot give an optimal solution.In this paper, a new methodology/pre-compiler is introduced, which speeds up loop kernels, by overcoming the above problems. This methodology solves four of the major scheduling sub-problems, together as one problem and not separately; these are the sub-problems of finding the schedules with the minimum numbers of (i) L1 data cache accesses, (ii) L2 data cache accesses, (iii) main memory data accesses, (iv) addressing instructions. First, the exploration space (possible solutions) is found according to the algorithm׳s information, e.g. array subscripts. Then, the exploration space is decreased by orders of magnitude, by applying constraint propagation to the software and hardware parameters.We take the C-code and the memory architecture parameters as input and we automatically produce a new faster C-code; this code cannot be obtained by applying the existing compiler transformations to the original code. The proposed methodology has been evaluated for five well-known algorithms in both general and embedded processors; it is compared with gcc and clang compilers and also with iterative compilation

Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management

“…Arrays with type2 subscript equations fetch their elements more than once, e.g., (2i + j = 7) holds for several iteration vectors (data reuse); on the other hand, equations of type1 fetch their elements only once; in [Kelefouras et al 2015], a new com-Parsing (); Extract the application characteristics () ; Transform all the array subscripts into math. equations (); for i=1, num of all different iterators nesting level values (loop interchange) for j=1, num of loop kernels Apply loop tiling to all the iterators (); Subsect.…”

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

“…Arrays with type2 subscript equations are accessed more than once from memory (data reuse), e.g., (2i + j = 7) holds for several iteration vectors; on the other hand, equations of type1 fetch their elements only once; in [50], I give a new compiler transformation that fully exploits data reuse of type2 equations. However, both type1 and type2 arrays may be accessed more than once in the case that the loop kernel contains at least one iterator that does not exist in the subscript equation, e.g., consider a loop kernel containing k, i, j iterators and B[i, j] reference; B[i, j] is accessed as many times as k iterator indicates.…”