A Methodology for RF modeling of packages with external pin measurements

Abstract

This article presents a methodology that allows the determination of the matrix representation of a package. The methodology is based on a set of calibration measurements, picked up at the external pins of the package, of a set of known integrated circuits. The representation of the package can be used both for a correct measurement of the embedded devices and to improve the design of integrated circuits. The effectiveness of the technique is demonstrated by the de-embedding of a packaged passive integrated inductor and the design of a low noise amplifier. The measurement sets were obtained through computer simulations. The effects of added noise on data, like measurement errors, are also investigated, and an approximate methodology, able to reduce these effects, is suggested

External Identification of a Reciprocal Lossy Multiport Circuit under Measurement Uncertainties by Riemannian Gradient Descent

“…In the research paper [17], it is assumed that the 2n-port network representing the electronic chip package/connector is reciprocal, implying the symmetry of the admittance matrix Y; namely, that Y EE = Y EE , Y II = Y II and Y IE = Y EI , where the superscript denotes matrix transposition. As a consequence, the Equation (3) simplifies into…”

“…, 4 of five corresponding measurements at the external pins of the electronic chip package/connector are available, the three matrix blocks Y EE , Y EI and Y II that perfectly fit the data can be found. Le us recall the closed-form solution proposed in [17].…”

“…In summary, the complete solution to the multiport identification problem as proposed in [17] is given by:…”

“…As a specific application, to exemplify the usefulness of multiport identification, consider the electronic chip-package de-embedding problem. This problem was tackled for a three-port network in [16] and for a general n-port network in [17]. The plastic package/connector of semiconductor-based electronic chips embeds a number of highly conductive wires whose function is to connect the internal electronic chip to the external pins.…”

“…In [17], the electronic chip package was modeled as a reciprocal, linear, time-invariant multiport network, which is supposed to be accessible using n internal electrical ports and n external electrical ports. The identification of the model, represented through a 2n × 2n admittance matrix Y, may be carried out by measuring the admittance of the external ports using a vector network analyzer.…”