A Methodology for Efficient Tile Size Selection for Affine Loop Kernels

Kelefouras, Vasilios; Djemame, Karim; Κεραμίδας, Γεώργιος; Nikolaos, Voros

doi:10.1007/s10766-022-00734-5

Cited by 2 publications

(1 citation statement)

References 34 publications

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“…Applying loop tiling to d-loop is not efficient, as first, the out array is loaded and stored multiple times in this case, second, the tiles of in contain non-consecutive memory locations (with the current layout) and thus they cannot entirely fit into the cache [25]. k.y/k.x loops are too small for applying tiling.…”

Section: Parallelization Loop Tiling and Loop Permutationmentioning

confidence: 99%

Design and Implementation of Deep Learning 2D Convolutions on Modern CPUs

Kelefouras,

Keramidas

2023

IEEE Trans. Parallel Distrib. Syst.

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In this paper, a new method is provided for accelerating the execution of convolution layers in Deep Neural Networks. This research work provides the theoretical background to efficiently design and implement the convolution layers on x86/x64 CPUs, based on the target layer parameters, quantization level and hardware architecture. The proposed work is general and can be applied to other processor families too, e.g., Arm. The proposed work achieves high speedup values over the state of the art, which is Intel oneDNN library, by applying compiler optimizations, such as vectorization, register blocking and loop tiling, in a more efficient way. This is achieved by developing an analytical modelling approach for finding the optimization parameters. A thorough experimental evaluation has been applied on two Intel CPU platforms, for DenseNet-121, ResNet-50 and SqueezeNet (including 112 different convolution layers), and for both FP32 and int8 input/output tensors (quantization). The experimental results show that the convolution layers of the aforementioned models are executed from x1.1 up to x7.2 times faster.

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Section: Parallelization Loop Tiling and Loop Permutationmentioning

confidence: 99%

Design and Implementation of Deep Learning 2D Convolutions on Modern CPUs

Kelefouras,

Keramidas

2023

IEEE Trans. Parallel Distrib. Syst.

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Enhancing Programs Efficiency through a Machine Learning-Based Model for Tile Size Selection

Ahmed,

Alwan,

Fanfakh

2024

BIO Web Conf.

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This work presents an innovative machine-learning approach to improve loop tiling in computational programming. Loop tiling is a crucial strategy for boosting speed by promoting data locality and reducing cache misses. Conventional methods frequently have difficulties in accurately calculating the most suitable tile size, which is a crucial component impacting the performance of the program. The combination of Multi-Output Generalized Regression Neural Networks (MOGRNN) and Linear Regression in researchers’ techniques allows for precise prediction of optimal tile sizes for various computing workloads. The study entails an extensive gathering of data from 22 benchmark programs, which encompass a diverse set of computational patterns and issue sizes. This data collection is further enhanced by incorporating both static and dynamic program aspects. By employing meticulous preprocessing and doing dual-model analysis, the researchers’ approach effectively captures both linear and intricate non-linear correlations present in the data. The method’s usefulness in boosting prediction accuracy for ideal tile sizes and enhancing overall program performance has been demonstrated through extensive testing on an Intel Core i7 CPU. This novel approach provides a viable avenue for advanced study in code optimization approaches.

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A Methodology for Efficient Tile Size Selection for Affine Loop Kernels

Abstract: including the URL of the record and the reason for the withdrawal request.Noname manuscript No.

Cited by 2 publications

References 34 publications

Design and Implementation of Deep Learning 2D Convolutions on Modern CPUs

Design and Implementation of Deep Learning 2D Convolutions on Modern CPUs

Enhancing Programs Efficiency through a Machine Learning-Based Model for Tile Size Selection

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