A methodology for deep sub-0.25 μm CMOS technology prediction

Palankovski, V.; Belova, N. E.; Puchner, H.; Aronowitz, S.; Selberherr, S.

doi:10.1109/16.954473

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…3 and Fig. 4, respectively, which are in good agreement with experimental data [10]. Opposite to that, the Spectre model available in our Cadence Design software is calibrated for 0.35 µm technology and higher, and therefore, can be applied under this constraint.…”

Section: Circuit Simulationsupporting

confidence: 60%

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Demonstration of a slipstream simulation flow including device and circuit simulators

Angelov

Palankovski

Hristov

et al.

28th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2005.

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Section: Circuit Simulationsupporting

confidence: 60%

“…Process and device calibration is completed when the threshold voltage-gate length characteristic (V Th -L g ) obtained by device simulation (Fig. 1) matches experimental data which indicates that the simulation includes advanced device behavior such as the reverse short channel effect [10].…”

Section: Technology and Device Simulationmentioning

confidence: 98%

Demonstration of a slipstream simulation flow including device and circuit simulators

Angelov

Palankovski

Hristov

et al.

28th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2005.

Self Cite

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“…The results are used in the calculation of SNM for the SRAM with different devices. To consider the quantum mechanical effects in the mixed-mode simulation, 3D density-gradient is solved together with the drift-diffusion transport model for electrical characteristics of planar MOSFETs and SOI FinFETs [13,14,15,17,20]. The computed device characteristics are connected to the SRAM's circuit simulation.…”

Section: Simulation Methodologymentioning

confidence: 99%

“…1a, is examined with a mixedmode simulation. The three-dimensional (3D) device simulation is performed to calculate device current-voltage (I − V ) characteristics by solving a set of density-gradient drift-diffusion equations [13,14] in the solution of coupled device and circuit equations [15,16,17]. For SRAM with the 32nm planar MOSFETs and SOI FinFETs, shown in the insets of Fig.1b, SNM is explored and compared.…”

Section: Introductionmentioning

confidence: 99%

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Hwang

2007

Computational Science – ICCS 2007

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Abstract. We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (σSNM ) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower σSNM . Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.

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“…In this work, we propose to perform mixed-mode simulations, which bring the process-simulated devices directly into the netlist of a circuit wherein both circuit and device equations are solved simultaneously. This technique has the advantage of being accurate as it has been pointed out in [9] that SPICE parameters may not capture the device behavior very accurately in the DSM regime. Further, the circuit-delay variation can be related directly to process parameter.…”

Section: Introductionmentioning

confidence: 99%

Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations

Srinivasaiah

Bhat

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Process, device, and mixed-mode (device/circuit) simulation-based approach is presented for 0.1-m gate length CMOS technology optimization and sensitivity analysis. The disposable spacer-based 0.1m NMOS and PMOS transistors with excellent short channel characteristics are designed using process and device simulations. The implant-dose sensitivity of the device parameters around the nominal value are estimated. The halo implant and super steep retrograde channel implant dose fluctuations are found to have a profound effect on device characteristics. It is shown that the mixed-mode device/circuit simulation can be used as an excellent tool to connect the circuit delay sensitivity to underlying process parameters. The simulation results demonstrate that the relation between circuit and process parameters is highly nonlinear for the deep submicron technology.

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A methodology for deep sub-0.25 μm CMOS technology prediction

Cited by 5 publications

References 6 publications

Demonstration of a slipstream simulation flow including device and circuit simulators

Demonstration of a slipstream simulation flow including device and circuit simulators

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations

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