A methodology for correct-by-construction latency insensitive design

Abstract

In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionally equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.

A Framework for Modeling the Distributed Deployment of Synchronous Designs

“…Latency-insensitive protocols were proposed in [11] and, then, applied to synchronous hardware design in [10,12]. A complete presentation of latency-insensitive design is given in [9], which includes a detailed discussion of the analysis and optimization of latencyinsensitive systems.…”

“…The application of latency-insensitive design to integrated circuits provides two main advantages [10]: (a) it enables the a-posteriori automatic pipelining of long wires by insertion of special patient processes called relay stations; (b) it facilitates the assembly of pre-designed components, that, as long as they are stallable, can be interfaced to the communication protocol without changing their internal structure. Assume that each process of Example 2 is implemented as a distinct finite state machine (FSM) on an integrated circuit and that the wire carrying signal x from Q to R is the only one that has been pipelined by introducing one relay station.…”

Throughput enhancement for repetitive internal cores in latency-insensitive systems

“…In system graphs that include multiple SCCs, the implementation of the protocol can be checked by two inequalities (1) and (2). In system graphs that include DAG, the implementation of the protocol can be checked by (5). The implementation techniques of the system were discussed with respect to (4) in two approaches.…”

“…Several methods have been implemented to compensate wire delays by wire pipelining [3,4]. Carloni was the first pioneer who introduced a correct-by-construction method to solve the wire delay problem [5]. This method is known as latencyinsensitive-protocol (LIP).…”

“…It simplifies building complex SoC by utilising predesigned IP cores. The only requirement for the latency-insensitive design (LID) is the ability to stall blocks that can be performed easily by gated clock mechanisms [5]. The LIP ensures that wire delays are not more than one clock period by inserting buffers in the wires that are named relay stations (RS).…”