A methodology for automated behavioral verification of floating-point designs

Kannappan, K.; Herbeck, G.H.; Stearns, C.C.

doi:10.1109/asic.1992.270216

Cited by 1 publication

(2 citation statements)

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“…One advantage of the proposed algorithm, is that it does not require bit level analysis or creating Cartesian equations and developing a particular engine to solve these equations as in [2], [3], [5], [10], [11]. Our constraints are word level constraints and are applied on existing SV constraint solvers.…”

Section: Evaluation Resultsmentioning

confidence: 99%

“…The authors in [2], [3] introduce a tool called FPgen that generates random tests based on defining coverage models relating the inputs, intermediate results and the outputs. Two behavioral tools are developed in [5]: vecgen generates test vectors based on input specification file and fpc defines a model based on the IEEE standard in [1], these two tools are integrated and simulated together to form an automatic verification for FP units.…”

Section: Introductionmentioning

confidence: 99%

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Binary floating point verification using random test vector generation based on SV constraints

Nouh

Fahmy

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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Verification of Binary Floating Point (FP) Arithmetic requires robust techniques to prove compliance with Floating point IEEE Standard (IEEE Std 754-2008). This paper provides a new verification methodology that uses a constraint based random technique to generate test vectors for validating FP arithmetic instructions. The new proposal is generic and can be used to verify any software or hardware binary FP design. The constraints used in verification are written in System Verilog (SV) language and can be solved with any SV constraint solver tool. The paper provides a case study to prove the feasibility and usefulness of the proposed approach in finding bugs for Addition-Subtraction and Multiplication operations.

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