A methodology and tool suite for C compiler generation from ADL processor models

Hohenauer, Manuel; Scharwaechter, Hanno; Karuri, Kingshuk; Wahlen, Oliver; Kogel, Tim; Leupers, Rainer; Ascheid, Gerd; Meyr, H.; Braun, Gunnar; Someren, Hans van

doi:10.1109/date.2004.1269071

Cited by 30 publications

(28 citation statements)

References 8 publications

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“…LISA does not have efficient compiler. A C compiler generator tool for LISA-modeled architecture has been proposed [9], [10]. Unfortunately, the assembly code generated by this compiler is less efficient than the one generated by the conventional GPP compiler.…”

Section: Copyright C 2014 the Institute Of Electronics Information Amentioning

confidence: 99%

Retargeting Derivative-ASIP with Assembly Converter Tool

Bejo

Isshiki

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.

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Section: Copyright C 2014 the Institute Of Electronics Information Amentioning

confidence: 99%

Retargeting Derivative-ASIP with Assembly Converter Tool

Bejo

Isshiki

et al. 2014

IEICE Trans. Inf. & Syst.

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“…(iii) Behavioural information generation based: Recognising that the architecture information needed by the compiler is not always in a form that may be well suited for other tools (such as synthesis) or does not permit concise specification, some research has focused on extraction of such information from a more amenable specification. Examples include the MSSQ and RECORD compiler using MIMOLA [8], the retargetable C compiler based on LISA [43], and the EXPRESS compiler using EXPRESSION [24]. MSSQ translates Pascal-like high-level language (HLL) into microcode for micro-programmable controllers, while RECORD translates code written in a DSP-specific programming language, called data flow language (DFL), into machine code for the target DSP.…”

Section: Compilersmentioning

confidence: 99%

“…MSSQ translates Pascal-like high-level language (HLL) into microcode for micro-programmable controllers, while RECORD translates code written in a DSP-specific programming language, called data flow language (DFL), into machine code for the target DSP. The retargetable C compiler generation using LISA is based on reuse of a powerful C compiler platform with many built-in code optimisations and generation of mapping rules for code selection using the instruction semantics information [43]. The EXPRESS compiler tries to bridge the gap between explicit specification of all information (e.g.…”

Section: Compilersmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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“…We use the C compiler generation technique described in [12] that bridges the gap between the LISATek tools for ASIP design [5] and the CoSy compiler generation platform [4]. From a single target processor model, given in the LISA 2.0 architecture description language (ADL), a complete software development tool chain (C compiler, ISS, assembler, etc.)…”

Section: System Overviewmentioning

confidence: 99%

“…can be generated. The Compiler Designer tool [12] extracts a compiler-oriented view from a given LISA 2.0 ADL model and transforms it into a custom specification format. On this specification, CoSy is invoked as a "backend" to generate the compiler executable.…”

Section: System Overviewmentioning

confidence: 99%

Retargetable code optimization with SIMD instructions

Schumacher

Ascheid

Meyr

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequent concern about retargetable compilers, though, is their lack of machine-specific code optimization techniques in order to achieve highest code quality. While this problem is partially inherent to the retargetable compilation approach, it can be circumvented by designing flexible, configurable code optimization techniques that apply to a certain range of target architectures. This paper focuses on target machines with SIMD instruction support which is widespread in embedded processors for multimedia applications. We present an efficient and quickly retargetable SIMD code optimization technique that is integrated into an industrial retargetable C compiler. Experimental results for the Philips Trimedia processor demonstrate that the proposed technique applies to real-life target machines and that it produces code quality improvements close to the theoretical limit.

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A methodology and tool suite for C compiler generation from ADL processor models

Cited by 30 publications

References 8 publications

Retargeting Derivative-ASIP with Assembly Converter Tool

Retargeting Derivative-ASIP with Assembly Converter Tool

Processor Description Languages

Retargetable code optimization with SIMD instructions

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