A method to improve the transient response of dq -frame cascaded delayed-signal-cancellation PLL

Xie, Ming; Wen, Huiqing; Zhu, Canyan; Yang, Yong

doi:10.1016/j.epsr.2017.10.004

Cited by 11 publications

(10 citation statements)

References 24 publications

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“…In order to further verify the transient response performance of the proposed PLL, the state-of-the-art PLL methods based on DSC technology in the recent 3 years are also compared. They are αβ CDSC-PLL(Semi-adaptive) in [14], CDSC-PLL PI (With DC removal) in [29] and dqCDSC3-PLL(with CPLC3) in [17]. Based on the experiments in this paper, the dynamic adjustment time of these four methods when a +5Hz frequency jump occurs are compared.…”

Section: E Simulation and Experimental Results Analysismentioning

confidence: 99%

“…According to (17), DNANF can be written in the form of a complex transfer function, so the expression of DNANF's transfer function is as follow:…”

Section: Dnanf With DC Offset Rejection Capabilitymentioning

confidence: 99%

“…To eliminate different harmonic components in the grid voltage, many DSC methods have been proposed by some scholars [14]- [16]. dqDSC-PLL proposed in [17] adopts a method of cascading multiple DSC operators with different time delays to achieve specific filtering effects in dq-frame. [18] proposed an improved frequency adaptive DSC-PLL structure to make the PLL adapting to grid voltage frequency changes.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

et al. 2020

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The phase-locked accuracy of conventional phase-locked method is reduced when the grid voltage contains fundamental frequency negative sequence(FFNS) component, harmonic component, and DC offset component. Aiming at this problem, a novel adaptive notch filter (NANF) is proposed, and a dual NANF (DNANF) structure is designed to eliminate the FFNS component and extract the fundamental frequency positive sequence(FFPS) component based on NANF. Furthermore, dcDNANF with DC offset rejection capability is proposed by adopting DNANF. Then a novel hybrid filter in dq-frame is designed by combining dcDNANF and the cascaded delay signal cancellation operator filter whose delay parameters are 4 and 24 in dq-frame (dqCDSC 4,24). Meanwhile, a new SRF-PLL design method is proposed based on the novel hybrid filter. This proposed method employs dqCDSC 4,24 to separate the positive and negative sequences of the voltage and eliminate the high frequency harmonics in the grid voltage, and uses dcDNANF to reject the DC offset, so as to achieve the accurate acquisition of the fundamental voltage information under distortion and unbalanced grid. Simulation and experimental results show that compared with the conventional SRF-PLL methods, the proposed method can obtain faster phase tracking speed, better phase-locked effect, faster dynamic response, and better stability. INDEX TERMS Novel adaptive notch filter (NANF), harmonic, phase-locked loop (PLL), dc offset, cascaded delay signal cancellation (CDSC).

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Section: E Simulation and Experimental Results Analysismentioning

confidence: 99%

“…According to (17), DNANF can be written in the form of a complex transfer function, so the expression of DNANF's transfer function is as follow:…”

Section: Dnanf With DC Offset Rejection Capabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

et al. 2020

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“…The presence of the dc offset in the input signal of these PLLs is always negligible. Unfortunately, the dc offset in the PLLs input, not only introduces the fundamental frequency oscillations in the estimated phase and frequency [10], but also may result in the dc injection by the grid-tied converters. The reason is that, these converters take for creating their reference current, often contain a dc component from the conventional PLLs [11].…”

Section: Introductionmentioning

confidence: 99%

A Simple Approach to Reject DC Offset for Single-Phase Synchronous Reference Frame PLL in Grid-Tied Converters

Liu

Wang

et al. 2020

IEEE Access

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Synchronous reference frame phase-locked loop (SRF-PLL) is widely used for grid voltage synchronization in single-phase grid-connected power converters. However, in the actual situation, dc offset component may be introduced in the input of the PLL, due to the transient fault of the power grid, sampling and measurement error, or A/D signal processing. A simple yet effective approach with additional all-pass filter based dc rejecter is presented for SRF-PLL, in this paper. Thereby, correct estimation and undesirable periodic ripple free can be achieved in SRF-PLL, when the input signal contains dc offset. The second order generalized integrator based PLL (SOGI-PLL) is first introduced, followed by the analysis on influence of the input dc offsets in SRF-PLL. The structure of enhanced-SOGI (ESOGI) with its analysis of dc offset rejection effects and performance have been then formulated in detail. Finally, experimental results are presented to demonstrate the effectiveness of the proposed ESOGI based PLL. INDEX TERMS DC offset, inverters, phase-locked loop (PLL), second order generalized integral.

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“…SRF-PLL can achieve good tracking results under the ideal power grid, but under the unbalanced and distorted conditions, the tracking performance of the ideal grid phase-locked loop will be affected due to the existence of fundamental frequency negative sequence voltage and high-frequency harmonics [12]. Therefore, many improved phase-locked loop techniques have been proposed [13]- [15]. In [16], the adaptive notch filter (ANF) was used to generate orthogonal signals in the synchronous rotating frame to complete the fundamental frequency positive and negative sequence voltage separation, and the design was suitable for the phase-locked loop under the unbalanced power grid.…”

Section: Introductionmentioning

confidence: 99%

Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

2020

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In the new energy grid-connected power generation system, accurately extracting the grid synchronization signals such as the frequency, phase and amplitude of the grid voltage is the basis for effective control. Aiming at the requirements for detecting grid synchronization signals under unbalanced, harmonics and DC offset voltage mixed conditions, a dual second-order complex coefficient filter with DC offset rejection capability (DSOCCF dc) is proposed, combining the approach of moving average filter (MAF), a novel hybrid filter in dq-frame is designed and on the basis of this design a new synchronous reference frame phase locked loop (SRF-PLL) design approach based on the hybrid filter is proposed. The proposed approach employs moving average filter (MAF) to block the high-frequency harmonics in the grid voltage, and uses DSOCCF dc to separate the fundamental frequency positive and negative sequence and reject DC offset. It can accurately extract the synchronization information of the grid fundamental frequency positive sequence. After simulation and experiment verification, it can be confirmed that the proposed PLL can quickly and accurately lock the properties of the grid voltage under adverse grid condition, and also have high detection accuracy and strong robustness to frequency fluctuations. INDEX TERMS Dual second-order complex coefficient filter (DSOCCF), harmonic, phase-locked loop (PLL), dc offset, moving average filter (MAF).

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A method to improve the transient response of dq -frame cascaded delayed-signal-cancellation PLL

Cited by 11 publications

References 24 publications

A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

A Simple Approach to Reject DC Offset for Single-Phase Synchronous Reference Frame PLL in Grid-Tied Converters

Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

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