A Method of Quick Edge Detection Based on Zynq

Xie, Renchao; Feng, Xiaoqin

doi:10.1109/cciot45285.2018.9032641

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…We adopted the design scheme of ARM+FPGA. The hardware device is based on ZYNQ platform released by Xilinx Company, which includes Programmable Logic (PL) and Processing System (PS) [46]. The PL side is based on FPGAs, and the PS side is based on a high-performance processor of ARM Cortex A53.…”

Section: Hardware Implementationmentioning

confidence: 99%

Hardware-Optimized Architecture of On-Board Registration for Remote-Sensing Images —Take SURF as an Example

Du,

Yang,

Zhong

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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On-board processing has become an inevitable choice for the development of remote sensing satellites. For the satellites with dual-line array asynchronous push-broom mode, image registration is crucial for pixel localization and alignment between dual-band strip data. However, due to the high computational complexity of feature detection and feature extraction, it is still a challenge to realize real-time registration for on-board edge devices with limited computing power and power consumption. Therefore, this paper proposes a hardwareoptimized architecture with high-performance and low-energy for on-board registration based on "ARM+FPGA". On one hand, optimized methods for the image registration algorithm are proposed from both software and hardware perspectives, providing a solution for on-board registration. On the other hand, in the face of the current interface environment of satellites, a design scheme for versatile hardware architecture is proposed. It provides a foundational technical route for hardware deployment of on-board processing. Experimental results show that in this hardware-accelerated architecture, the average acceleration effect of registration algorithm can reach 15 times compared to the unoptimized version. Additionally, the average power consumption is reduced by 60%, and the hardware resource utilization is less than 40%. Importantly, the algorithm's accuracy remains unaffected by these optimizations. The onboard intelligent processing payload deployed with this hardware architecture has been successfully launched and validated in February 2022 in the orbit of the MN200Sar-1 satellite from China. It improves the real-time capability for on-board processing, and aims to achieve a new imaging mechanism where target and information transmission replace strip image transmission. Index Terms-Field Programmable Gate Array (FPGA), Hardware acceleration, On-board processing, Speed-up Robust Features (SURF), High-Level Synthesis (HLS).

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Section: Hardware Implementationmentioning

confidence: 99%

Hardware-Optimized Architecture of On-Board Registration for Remote-Sensing Images —Take SURF as an Example

Du,

Yang,

Zhong

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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“…Sobel algorithm [6] ~8ms@PC, ~66ms@ OpenCV ~4.17ms @ xfOpenCV Canny alg., Zynq7000 This work 656ms@Intel i7, 3.4GHz 9.24ms (kernels), 17.52ms(+transfer time) Sobel, Global mem., 512 data pack.…”

Section: Ref Comparison Proposed Solution Notesmentioning

confidence: 99%

“…On the other hand, the authors in [5] developed a Sobel Edge Detection algorithm on Xilinx Spartan-6 FPGA platform achieving better latency and higher operational frequency. In [6], a ZynqMP UltraScale MPSoC is used, focusing on the advantages of the xfOpenCV acceleration library to develop a faster Sobel Edge Detection method. In [7], the Vivado HLS v2015.3 tool is used and a comparison between software and hardware implementations of the Sobel Algorithm is presented.…”

Section: Introductionmentioning

confidence: 99%

Exploiting Vitis Framework for Accelerating Sobel Algorithm

Mousouliotis

Zogas

Christakos

et al. 2021

2021 10th Mediterranean Conference on Embedded Computing (MECO)

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Edge detection is one of the most common operations needed in the image processing domain. In this work, alternative implementations of the Sobel algorithm are tested on a ZCU102 Xilinx embedded platform, demonstrating how different optimization techniques can be conveniently configured in Xilinx Vitis environment. We exploit (a) Xilinx Runtime library (XRT) that allows the reprogramming of the reconfigurable logic at real time and (b) the various high-level attributes offered by the OpenCL API for efficient resource allocation in the state-of-the-art Xilinx Ultrascale Multi-Processor System-on-Chips (MPSoC). Specifically, different implementations of the Sobel algorithm (varying the data transfer models and data packing modes) are demonstrated and analyzed. Our experimental results shows that starting from a CPU implementation with 656 ms latency, the frame processing time is reduced to a range between 17 ms and 22 ms depending on the allocated resources, leading to a solution that is up to 38 times faster.

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