A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units

Abstract

This paper proposes new digital filter architecture based on a modified multiply-accumulate (MAC) unit architecture called truncated MAC (TMAC), with the aim of increasing the performance of digital filtering. This paper provides a theoretical analysis of the proposed TMAC units and their hardware simulation. Theoretical analysis demonstrated that replacing conventional MAC units with modified TMAC units, as the basis for the implementation of digital filters, can theoretically reduce the filtering time by 29.86%. Hardware simulation showed that TMAC units increased the performance of digital filters by up to 10.89% compared to digital filters using conventional MAC units, but were associated with increased hardware costs. The results of this research can be used in the theory of digital signal processing to solve practical problems such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

“…The maximum clock frequency of the proposed device is 31.03% -38.46% higher compared with device based on Winograd method [9] and 1.89% -2.94% higher compared to the filter based on MAC [23] units for the case of 8-and 16-bit devices, but 26.21% less for the case of 8-bit devices. Nevertheless, in comparison with the TMAC-based filter architecture in PNS [13] and in RNS [14] the performance of the proposed device is 7.89% -35.59% lower. The number of LUTs occupied by the proposed device is 18.08% -37.27% less compared with the filter based on Winograd method [9], but 3.83 -7.74 times more compared to other reviewed known architectures.…”

“…In addition, the proposed device architecture has 13.47% -42.04% less delay, and 2.20% -18.03% less area, except for the 8-bit device, which has a 47.38% larger area than the known MAC-based filter architecture [23]. Compared to the known device architecture based on TMAC units with computations in PNS [13] the delay of the proposed device is 20.92% -22.22% less, but the area is 1.56% -53.37% more for 8-and 16-bit devices, and for 32-bit devices, the delay is 12.17% larger, but the area is 18.03% less. The proposed architecture of the 8-bit filter has 2.15% lower latency, but 16-and 32-bit devices have 3.42% -52.52% more delay, compared to the known architecture based on TMAC units with computations in RNS.…”

“…The paper [13] presents truncated MAC blocks (TMAC), the filter parameters for 2 × 2 filter mask, consisting of these units are calculated as follows:…”

“…The proposed architecture bases on ternary value logic and RNS, however using this approach leads to the high complexity of converting between ternary value logic and RNS. The authors of the paper [13] proposed a filter architecture with finite impulse response based on truncated MAC units (TMAC). In [14], the implementation of TMAC units in RNS with moduli of a special type 2 α and 2 α − 1, α ∈ N, where N is the natural numbers set.…”

High-performance digital image filtering architectures in the residue number system based on the Winograd method

“…В работе [14] авторы предлагают новое устройство умножения с накоплением. Авторы статьи [15] представили новое усеченное устройство умножения с накоплением для реализации цифровых фильтров с конечной импульсной характеристикой.…”