A method for negative bias temperature instability (NBTI) measurements on power VDMOS transistors

Abstract

A method suitable for performing NBTI measurements on power p-channel VDMOS transistors is described. A practical implementation using simple boosting circuit for obtaining required gate stress voltage and sweep I–V measurements for the threshold voltage shift determination is presented. Experimental results are discussed in terms of the time necessary to perform interim measurements during NBTI tests. It is shown that the measurements could be done fast enough to capture part of the dynamic recovery effect in these devices, which is important for the lifetime prediction.

Effects of pulsed negative bias temperature stressing in p-channel power VDMOSFETs

“…The devices were built in standard Si-gate technology with gate oxide thickness of 100 nm, and had the initial threshold voltage, V T0 , about 3.6 V. Owing to the thick gate oxide, accelerated NBT stressing of these devices requires gate stress voltage amplitudes even over -40 V, which exceed capabilities of commonly used signal voltage sources [22], [23]. For that reason we have developed a specific stress and measurement system suitable for NBTI testing in power MOS devices, which includes an external amplifier between the stress voltage source unit and the device under test (DUT) [24]. The system actually includes high voltage stress circuit and the low voltage measurement circuit, which are separated by two software-controlled switches.…”

“…All the instrumentation and the temperature inside the Heraeus HEP2 chamber are computer controlled over IEEE-488 GPIB bus. This setup provides a complete measurement of I-V characteristic, with gate voltage swept from 4.75 V to 2 V in 50 mV steps, in about 235 ms (including the time required to switch the circuits from stress to measurement and back), which practically means that DUT remains unstressed at least 235 ms for each interim measurement performed [24].…”

Modeling and PSPICE simulation of NBTI effects in VDMOS transistors

“…1 shows experimental transfer characteristics of transistor during NBT stressing at negative gate voltage of V GS = -40 V (electric field in the oxide E ≈ 4 MV/cm) and temperature of 150°C. For measurement of the transfer characteristics during NBT stressing, the system presented in details in [12] is used.…”

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET

“…Having in mind the above mentioned, we have recently developed stress and measurement technique based on costeffective switching circuit, which provides reasonable compromise between stress and measurement requirements and is suitable for NBT stress and measurements on VDMOS transistors. [31,32] Our measurement technique has been verified by a series of NBTI tests on several devices. [31][32][33] As an example, figure 1 shows measured transfer I-V characteristics for a VD-MOS device subjected to 24 h of the pulsed NBT stress at V G = −45 V, T = 175 • C, f = 18.82 kHz, DTC = 94.12%.…”

“…[31,32] Our measurement technique has been verified by a series of NBTI tests on several devices. [31][32][33] As an example, figure 1 shows measured transfer I-V characteristics for a VD-MOS device subjected to 24 h of the pulsed NBT stress at V G = −45 V, T = 175 • C, f = 18.82 kHz, DTC = 94.12%. During the 24-h test, the total of 37 interim measurements were performed according to the predefined timeline, but for simplicity only a few transfer I-V characteristics are shown.…”