A method for efficient Radiation Hardening of multicore processors

Ballast, Jon; Amort, Tony; Cabanas-Holmen, Manuel; Cannon, Ethan H.; Brees, Roger; Neathery, Charles; Fischer, Steve; Snapp, Warren P.

doi:10.1109/aero.2015.7119216

Cited by 3 publications

(4 citation statements)

References 15 publications

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“…For example, Eqs. (16)(17)(18)(19)(20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30) demonstrate the process of calculating device metrics for the Xilinx Virtex ® -5 FX130T, which is an FPGA [24-27]. CD calculations require information about the total available logic resources of the architecture in terms of flip flops, lookup tables, and digital-signal-processing units.…”

Section: Device Metrics Methodologymentioning

confidence: 99%

“…As shown in Eqs. (16)(17)(18)(19)(20), the CD is calculated separately for each integer and floating-point data type, based upon the operating frequencies and logic resources used for additions and multiplications, where each computational unit can compute one operation per cycle and multiple versions of each computational unit are considered that make use of different types of logic resources. CD/W calculations require the use software tools to generate information about power dissipation given the configuration of computational units for each data type [27].…”

Section: Device Metrics Methodologymentioning

confidence: 99%

“…Space-grade processors must be radiation hardened or radiation tolerant to withstand cumulative radiation effects such as charge buildup within the gate oxide that causes damage to the silicon lattice over time, and they must provide immunity to single-event effects that occur when single particles pass through the silicon lattice and cause errors that can lead to data corruption or disrupt the functionality of the processor [13][14][15]. Several techniques exist for the fabrication of space-grade processors [16][17][18], including radiation hardening by process, which involves the use of an insulating oxide layer, and radiation hardening by design, which involves specialized transistor-layout techniques. Although both space-grade and COTS processors can be used in space, space-grade processors are often necessary, depending on the mission's orbit or location, planned lifetime, and requirements for reliability and accessibility.…”

Section: Background and Related Researchmentioning

confidence: 99%

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Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

Lovelly

George

2017

Journal of Aerospace Information Systems

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Due to harsh and inaccessible operating environments, space computing presents many unique challenges and constraints that limit onboard computing performance. However, the increasing need for real-time sensor and autonomous processing, coupled with limited communication bandwidth with ground stations, is increasing onboard computing demands for next-generation space missions. Because currently available space-grade processors cannot satisfy this growing demand, research into various processors is conducted to ensure that potential new processors are based upon architectures that will best meet the computing needs of space missions. Device metrics are used to measure and compare the theoretical capabilities of processors based upon vendor-provided data and tools, enabling the study of large and diverse sets of architectures. Architectural tradeoffs are determined that can be considered when comparing or designing space-grade processors. Results demonstrate how onboard computing capabilities are increasing due to emerging architectures that support high levels of parallelism in terms of computational units, internal memories, and input/output resources; and that performance varies between applications, depending on the compute-intensive kernels used. Furthermore, the overheads incurred by radiation hardening are quantified and used to analyze low-power commercial-off-the-shelf processors for potential hardening and use in future space missions.

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Section: Device Metrics Methodologymentioning

confidence: 99%

Section: Device Metrics Methodologymentioning

confidence: 99%

Section: Background and Related Researchmentioning

confidence: 99%

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Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

Lovelly

George

2017

Journal of Aerospace Information Systems

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“…Radiation Hardening By Design (RHBD) techniques have been demonstrated to provide robust performance at sub-100 nm process nodes where radiation hardened processes do not exist. Consequently, RHBD enables unprecedented designs for high radiation environments, such as satellite applications, that capitalize on the benefits of scaling, such as RHBD multi-core processors [20].…”

Section: Realizing the Future Of Aerospace Through Resilient Ic Dmentioning

confidence: 99%

Resiliency challenges in sub-10nm technologies

Aitken

Cannon

Pant

et al. 2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Improvements in chip manufacturing technology, driven by high degree of integration due to small device sizes and additional complex functionalities enabled by heterogeneous integration, have propelled an astonishing growth of computing systems. While the pervasiveness of these systems enables emerging application domains, however, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and resiliency of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process, while other factors appear because of high frequencies and nanoscale features. This paper overviews the vision by some of the key industrial players regarding the emerging resiliency challenges faced at the extreme nanoscale technologies. IEEE 33rd VLSI Test Symposium (VTS)978-1-4799-7597-6/15/$31.00 ©2015 IEEE

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