A memory system design framework

Firoozshahian, Amin; Solomatnikov, Alex; Shacham, Ofer; Asgar, Zain; Richardson, Stephen; Kozyrakis, Christos; Horowitz, Mark

doi:10.1145/1555754.1555805

Cited by 22 publications

(6 citation statements)

References 17 publications

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“…The model's growth is attributed to the fact that incorporating more items attributes arXiv:2402.04032v3 [cs.AR] 14 Mar 2024 to better model quality [13], [14]. However, the model operating on the inference server [5], [15], [16], [17] is significantly smaller in scale compared to the training model [13], [14]. Therefore, a significant gap exists between the training model size and the inference model size.…”

Section: Introductionmentioning

confidence: 99%

A bibliometric analysis of publications by the School of Biological Sciences, Seoul National University, South Korea

Kim

2013

Scientometrics

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Section: Introductionmentioning

confidence: 99%

A bibliometric analysis of publications by the School of Biological Sciences, Seoul National University, South Korea

Kim

2013

Scientometrics

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“…Smart Memories is a chip multiprocessor with a memory system flexible enough to support traditional shared memory, streaming, and transactional memory programming models on the same hardware substrate [9] [10]. The system was designed to be a multiprocessor whose user could program not only the processors, but the memory system as well.…”

Section: Motivating Example: Smart Memories Protocol Controllermentioning

confidence: 99%

“…Sorin et al argue that a single table-driven approach can be used in many design phases, including specifying, documenting, and verifying cache coherence protocols [11]. Firoozshahian et al go a step further and describe how programmable, table-driven controllers can allow a memory controller to support different memory models and protocols within a CMP system [9]. However, these table-driven imple mentations come with significant area and cycle-time costs from the added memories and address decoding logic.…”

Section: Motivating Example: Smart Memories Protocol Controllermentioning

confidence: 99%

Intermediate representations for controllers in chip generators

Kelley

Wachs

Danowitz

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Creating parameterized "chip generators" has been proposed as one way to decrease chip NRE costs. While many approaches are available for creating or generating flexible data path elements, the design of flexible controllers is more prob lematic. The most common approach is to create a microcoded engine as the controller, which offers flexibility through pro grammable table-based lookup functions. This paper shows that after "programming" the hardware for the desired application, or applications, these flexible controller designs can be easily converted to efficient fixed (or less programmable) solutions using partial evaluation capabilities that are already present in most synthesis tools.

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“…This approach originated in associative processors [6] and active data structures [1]; other examples include priority queues [2], systems with chunks of memory organised as trees [15], smart memories for multicore processors [5], associative searching [9]. Circuit parallelism is the target platform for compilation of a declarative committed-choice rule language [16].…”

Section: Introductionmentioning

confidence: 99%

Extensible sparse functional arrays with circuit parallelism

O'Donnell

2013

Proceedings of the 15th Symposium on Principles and Practice of Declarative Programming

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A longstanding open question in algorithms and data structures is the time and space complexity of pure functional arrays. Imperative arrays provide update and lookup operations that require constant time in the RAM theoretical model, but it is conjectured that there does not exist a RAM algorithm that achieves the same complexity for functional arrays, unless restrictions are placed on the operations. The main result of this paper is an algorithm that does achieve optimal unit time and space complexity for update and lookup on functional arrays. This algorithm does not run on a RAM, but instead it exploits the massive parallelism inherent in digital circuits. The algorithm also provides unit time operations that support storage management, as well as sparse and extensible arrays. The main idea behind the algorithm is to replace a RAM memory by a tree circuit that is more powerful than the RAM yet has the same asymptotic complexity in time (gate delays) and size (number of components). The algorithm uses an array representation that allows elements to be shared between many arrays with only a small constant factor penalty in space and time. This system exemplifies circuit parallelism, which exploits very large numbers of transistors per chip in order to speed up key algorithms. Extensible Sparse Functional Arrays (ESFA) can be used with both functional and imperative programming languages. The system comprises a set of algorithms and a circuit specification, and it has been implemented on a GPGPU with good performance.

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A memory system design framework

Cited by 22 publications

References 17 publications

A bibliometric analysis of publications by the School of Biological Sciences, Seoul National University, South Korea

A bibliometric analysis of publications by the School of Biological Sciences, Seoul National University, South Korea

Intermediate representations for controllers in chip generators

Extensible sparse functional arrays with circuit parallelism

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