A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform

Hu, Yusong; Jong, Ching Chuen

doi:10.1109/tcsii.2013.2268335

Cited by 30 publications

(42 citation statements)

References 19 publications

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“…In order to process an image of size MN, N Fig. 3, the number of image memory accesses is significantly reduced compared with the state-of-the-art architecture [11], resulting in higher energy efficiency and lower EAT as demonstrated in Section IV.C. Note that in practical applications, a design with small S can offer enough throughput (S ≤ 3).…”

Section: B Overlapped Block-based Scanning Methodsmentioning

confidence: 99%

“…On the other hand, the external memory bandwidth is significantly increased. The state-ofthe-art architecture for single-level DWT is presented in [11], where the temporal memory size is reduced to 3N at the expense of one pixel overlap between two adjacent stripes.…”

Section: B Related Workmentioning

confidence: 99%

“…In this section, the proposed architecture and baseline architecture (state-of-the-art architecture in [11]) for 5/3, 9/7 DWT filter with various block and input image sizes are implemented. The energy efficiency and EAT are measured and compared.…”

Section: A Experimental Setupmentioning

confidence: 99%

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Energy- and area-efficient parameterized lifting-based 2-D DWT architecture on FPGA

Prasanna

2014

2014 IEEE High Performance Extreme Computing Conference (HPEC)

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State-of-the-art DWT designs focus on improving hardware utilization and memory efficiency of DWT. In this paper, we consider energy efficiency as the key performance metric. Memory (external memory and on-chip memory) energy dominates the total energy consumption. We propose a DWT architecture with an overlapped block-based image scanning method that optimizes the number of external memory accesses and the on-chip memory size. Using the overlapped block-based scanning method, the required number of external memory accesses of the proposed architecture is reduced by up to 50% when compared with state-of-the-art designs. Besides, the on-chip memory size is also reduced. We implement the proposed architecture on a state-of-the-art FPGA for various image sizes. Our design sustains up to 80.2% of the peak energy efficiency of the device. Compared with the state-of-the-art design, the proposed architecture achieves up to 58.1% energy efficiency improvement.

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Section: B Overlapped Block-based Scanning Methodsmentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

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Energy- and area-efficient parameterized lifting-based 2-D DWT architecture on FPGA

Prasanna

2014

2014 IEEE High Performance Extreme Computing Conference (HPEC)

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“…This architecture achieves the smallest memory size of 3n+24S. It has a constant latency and its TP is scalable by scaling the number S of Data Processing Pipe (DPP) in which a block of 2S pixels is processed every clock cycle [19]. B. K. Mohanty, et al, proposed a memory efficient architecture for 3-D DWT using overlapped grouping of frames and has a small cycle period, and offers small output latency.…”

Section: Literature Surveymentioning

confidence: 99%

VLSI Architectures for Lifting Based Discrete Wavelet Transform – A Survey

Kalaiarasi¹,

Vigneswaran²

2016

IJEECS

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“…Hu et at. [5] have implemented several parallel units in both row processor and column processor, achieving path delay of Ta + Tm with smaller size of the temporal memory of 3N. Zhang et at.…”

Section: Introductionmentioning

confidence: 99%

Memory efficient architectures for 2-D lifting-based discrete wavelet transform: A survey

Darkunde

Agrawal

2015

2015 International Conference on Industrial Instrumentation and Control (ICIC)

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The goal of this paper is to review recent developments in memory efficient VLSI architectures of the lifting based two dimensional discrete wavelet transform (DWT). The memory requirement and critical path delay are key points determining the efficiency of the architecture. In recent years, architectures have been developed to achieve balance between path delay and memory requirement. Memory requirement is also contributed by methods used for reading the data from the input image.Architectures with various data scanning methods are reviewed in this paper.

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A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform

Cited by 30 publications

References 19 publications

Energy- and area-efficient parameterized lifting-based 2-D DWT architecture on FPGA

Energy- and area-efficient parameterized lifting-based 2-D DWT architecture on FPGA

VLSI Architectures for Lifting Based Discrete Wavelet Transform – A Survey

Memory efficient architectures for 2-D lifting-based discrete wavelet transform: A survey

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