A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

Design of a Fast Multi-Reference Frame Integer Motion Estimator for H.264/AVC

“…The Huang's system [9] uses five reference frames, but the Chen's system [8], the Youn's system [10] and the Kao's system [11] use only one or two reference frames and require an additional control to use the modified algorithm. The Huang's system uses only 16x16 or 8x8 block sizes.…”

“…In particular, the integer pixel motion estimation module is one of the most time-consuming blocks, consuming 74.25% of the execution time in the H.264/AVC encoder [6]. Because the number of computations required for multi-reference frame motion estimation is very large, implementation of a real-time multi-reference integer motion estimation encoder is difficult, and most of the previous integer motion estimators used only one reference frame or two reference frames [7][8][9][10][11].…”

“…In terms of the experimental results, the modified algorithm shows a 0.36% bit-rate increase when compared with the five reference frame standard. The simulation result shows that the performance of the proposed system is better than that of FMASS [16], AFMFSA [17], FRFSA [18], the Huang's system [9], the Youn's system [10], the extension version of the Youn's system, and the Kao's system [11].…”

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

“…The bit-serial architecture in [22] uses a pipeline design, a reduced number of PEs and a pixel truncation technique to obtain a high clock frequency and low area cost but with a latency of 26 624 clock cycles. In [27], different memory-efficient, parallel 2-D architectures based on 16 Â 16 Â 16 PEs are analyzed. In Table 4, the proposed design (b) is depicted, Table 4 Comparison of the proposed processor with other IME designs.…”

“…References which adopt the complete FSBMA include the 2D architecture with a simple regular control in [16], the novel memory-access with minimum off-chip memory bandwidth in [19], the highperformance reconfigurable architecture to support a scan format for a high data reuse within the search area in [20], the bit serial architecture in [22] and the high throughput design in [39]. Modifications of the FSBMA to reduce either hardware or computing time, at the cost of introducing some video quality loss, can be found in the soft algorithm to simplify the predicted MV and the early termination of motion search used in [21], the multi-resolution IME algorithm presented in [23], the adaptive size in the search area depending on the degree of motion activity in [24,25], the modified algorithm to reduce hardware based on data dependency of motion vector prediction, pixel truncation and subsample proposed in [18], the IP with coarse and fine searches in [26] and the inter-candidate 4-parallel data reuse scheme with 16 2D PE-arrays in [27].…”