A measurement technique for ESD current spreading on a PCB using near field scanning

Huang, Wei; Pommerenke, David; Xiao, Jiang; Liu, Dazhao; Jin, Min; Muchaidze, Giorgi; Kwon, Soon‐Jae; Kim, Ki Hyuk

doi:10.1109/isemc.2009.5284636

Cited by 23 publications

(2 citation statements)

References 5 publications

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“…This is a vast improvement over the commonly known off-chip contact characterisation systems as electrically connected setups contain larger current loops, resulting in a larger mutual coupling and DUT bondwire inductances are in the order of nH [5,6]. Another advantage over known non-contact characterisation methods is that the presented technique provides accurate in situ information [7]. Conclusion: An innovative measurement method for on-chip ESDwaveform characterisation has been presented.…”

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confidence: 91%

Wideband measurement system for on-chip ESD waveform characterisation

et al. 2012

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In this age where new electronic designs are constantly pushing the limits of technology, there is a persistent need for better electrostatic discharge (ESD) protection. Proposed is a measurement probe architecture that can be used for on-chip ESD waveform characterisation. The probe circuit design is presented and test results show the feasibility of the proposed system. Such a measurement system provides invaluable information, aiding the electronics designer in the search for more robust chip designs.

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confidence: 91%

Wideband measurement system for on-chip ESD waveform characterisation

et al. 2012

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“…In ESD measurement, it is difficult to precisely determine the current paths in the DUT, while a pass or fail evaluation can be conducted. ESD gun models have been proposed for ESD standards at the simulation level [9]- [11], and fullwave 3D electromagnetic field simulation has been conducted for a PCB-level ESD analysis method [12]- [14]. A method for observing ESD waveforms when ESD enters through the input/output (I/O) pins of ICs has also been devised [15].…”

Section: Introductionmentioning

confidence: 99%

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging

Wadatsumi

Kawai

Hasegawa

et al. 2023

IEICE Trans. Electron.

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This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200 mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5 kΩ contact resistor on the backside of a 350 µm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40 µm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

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Soft Failure Mechanisms and PCB Design Measures

Pommerenke

Maheshwari

2015

System Level ESD Co‐Design

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A measurement technique for ESD current spreading on a PCB using near field scanning

Cited by 23 publications

References 5 publications

Wideband measurement system for on-chip ESD waveform characterisation

Wideband measurement system for on-chip ESD waveform characterisation

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging

Soft Failure Mechanisms and PCB Design Measures

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