A novel physics-based chip-scale surface profile model is proposed to focus on investigating the influence of the design pattern effects on the tungsten surface topography in the chemical mechanical planarization (CMP) process. The two-scale contact pressure computation method is constructed to obtain an accurate pressure distribution between the wafer surface and the polishing pad. The chip-scale contact mechanics-based global pressure has been first introduced to capture the long range height variation of W CMP caused by deposition and polishing processes. Then, the feature-scale pattern dependent effect is considered to accurately calculate the local contact pressure which is further integrated with the fundamental of steady-state oxidation reaction to construct a new material removal rate model used for simulation of surface height evolution. The model prediction results are consistent with the collected experimental data in predicting the dishing effect at different slurry conditions. The present CMP model can be utilized to assist in analyzing the influence of the design pattern effects on the wafer surface topography and be readily incorporated into a design for manufacturability flow to form a chip-scale planarity simulator to detect the hotspots of the entire design layout.