A Manifold Regularization Approach for Low Sampling Rate Digital Predistortion With Band-Limited Feedback

Jiang, Chengye; Qiao, Wen; Yang, Guichen; Su, Lei; Han, Renlong; Tan, Jingchao; Liu, Falin

doi:10.1109/tmtt.2022.3167669

Cited by 8 publications

(2 citation statements)

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“…Hence, the forward path’s DAC and the feedback path’s ADC are expected to operate at a sufficiently high sampling rate to accommodate signals with a bandwidth equal to

, where

refers to the bandwidth of the input signal. Several solutions have been proposed to relax the sampling rate of the ADC used in the feedback path [ 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 ]. This is possible since the in-band frequency range includes information about higher order distortions [ 8 ].…”

Section: Proposed Predistortion Systemmentioning

confidence: 99%

“…However, most research focused on reducing the sampling rates in either the forward or the feedback path separately, which limits their practicality. For instance, the works in [ 17 , 18 , 19 ] present a novel band-limited feedback approach to reduce the feedback path ADC sampling rate. This was effectively completed by utilizing a bandpass filter prior to the feedback path’s ADC and implementing varying forms of band-limited DPD functions.…”

Section: Introductionmentioning

confidence: 99%

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Power Amplifier Predistortion Using Reduced Sampling Rates in the Forward and Feedback Paths

Ahmed,

Bensmida

et al. 2024

Sensors

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The feasibility of implementing digital predistortion for next-generation wireless communication is faced with a dilemma due to the ever-increasing demand for faster data rates. This causes the utilized bandwidth to increase significantly, as seen in the 5G NR standard in which bandwidths as high as 400 MHz are utilized. Hence, the development of new predistortion techniques in which the forward and feedback paths operate at lower sampling rates is of utmost importance to realize efficient and practical predistortion solutions. In this work, a novel predistortion technique is presented by which the predistortion is divided between the digital and analog domains. The predistorter is composed of a memoryless AM/AM gain function that is implementable in the analog domain, and a nonlinear model with memory effects in the digital domain to relax the sampling rate requirements on both the forward and feedback paths. Experimental validation was carried out with a 20 MHz and a 40 MHz 5G signal, and the results indicate minimal linearization degradation with a sampling rate reduction of 50% and 30%, respectively. This sampling rate reduction is concurrently applied in the digital-to-analog converter of the forward path and the analog-to-digital converter of the feedback path.

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“…Hence, the forward path’s DAC and the feedback path’s ADC are expected to operate at a sufficiently high sampling rate to accommodate signals with a bandwidth equal to

, where