A magnetoelectronic register file cell for a self‐checkpointing microprocessor

Ryu

et al. 2012

SUMMARYThe conventional magnetic tunneling junction (MTJ)-based non-volatile D flip-flop (NVDFF) has a slow D-Q delay and a tradeoff between its D-Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ-based non-volatile semidynamic flip-flop (NVSDFF) has a semidynamic structure that ensures a fast D-Q delay and separates the sensing circuit from the D-Q signal path to reduce the sensing current without affecting the D-Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry-compatible 45 nm model parameter show that the D-Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller.

Section: Introductionmentioning

confidence: 99%

An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

Jung

Ryu

et al. 2012

“…Content addressable memories (CAMs) are widely used for data comparison and lookup tables for cache memory, network routers, and data compression . There are two types of CAMs: NOR CAM and NAND CAM .…”

Section: Introductionmentioning

confidence: 99%

Dynamic mixed serial–parallel content addressable memory (DMSP CAM)

Kang

Yang

et al. 2011

SUMMARYA novel dynamic mixed serial-parallel content addressable memory (DMSP CAM) is proposed to achieve both low-power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45-nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy-delay product reduction compared with the other serial-parallel mixed CAMs.

Sensing margin trend with technology scaling in MRAM

Song

Kang

et al. 2011

SUMMARYMagnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano-meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation.