A machine learning framework to identify detailed routing short violations from a placed netlist

Tabrizi, Aysa Fakheri; Rakai, Logan; Darav, Nima Karimpour; Bustany, Ismail; Behjat, Laleh; Xu, Shuchang; Kennings, Andrew

doi:10.1145/3195970.3195975

Cited by 29 publications

(22 citation statements)

References 20 publications

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“…Paper [12] is an enhancement of [11] in which the authors implemented parallel zonal search to reduce prediction time in the high terminal and high fan-out nets. The global routing-based congestion estimation models discussed in [5][6][7][8][9] work perfectly well on larger technology nodes, i.e., greater than 45nm. However, as the process technology size decreases, the miscorrelation between GR-based congestion prediction and actual detailed route congestion increases because of high pin density, complex DRC rules, and increased routing tracks per unit area.…”

Section: Related Literaturementioning

confidence: 93%

“…Machine Learning (ML) has found its application in various Electronic Design Automation (EDA) problems, and has been used to make early prediction on various quality related parameters. In EDA, ML finds its applications in yield prediction [1], timing [2,3] and power optimization [4], auto-tuning of CAD tool parameters [3], and routing congestion estimation [5][6][7]. Learning from prior designs and predicting performance and closure issues has immense value in the EDA community.…”

Section: Introductionmentioning

confidence: 99%

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Congestion Prediction in FPGA Using Regression Based Learning Methods

Goswami

Bhatia

2021

Electronics

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Design closure in general VLSI physical design flows and FPGA physical design flows is an important and time-consuming problem. Routing itself can consume as much as 70% of the total design time. Accurate congestion estimation during the early stages of the design flow can help alleviate last-minute routing-related surprises. This paper has described a methodology for a post-placement, machine learning-based routing congestion prediction model for FPGAs. Routing congestion is modeled as a regression problem. We have described the methods for generating training data, feature extractions, training, regression models, validation, and deployment approaches. We have tested our prediction model by using ISPD 2016 FPGA benchmarks. Our prediction method reports a very accurate localized congestion value in each channel around a configurable logic block (CLB). The localized congestion is predicted in both vertical and horizontal directions. We demonstrate the effectiveness of our model on completely unseen designs that are not initially part of the training data set. The generated results show significant improvement in terms of accuracy measured as mean absolute error and prediction time when compared against the latest state-of-the-art works.

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Section: Related Literaturementioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

Congestion Prediction in FPGA Using Regression Based Learning Methods

Goswami

Bhatia

2021

Electronics

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“…The presented solution, according to [7], is built on a novel real-time IoT routing algorithm, where generalised information decisions are utilised to increase the overall security and response time of IoT transmissions. In addition, the authors have developed a delay iterative method (DIM) to address the issue of missing valid routes, which is entirely based on delay calculations.…”

Section: Related Workmentioning

confidence: 99%

Network Lifetime Analysis in IOT Environment in Healthcare Sectors Using Deep Learning Routing Approach

Janaki

2021

Advances in Parallel Computing Technologies and Applications

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The Internet of Things (IoT) provides an improved flexibility in data collection, network deployment and data transmission to the sink nodes. However, depending on the application, the IoT network tends to consume lot of power from the individual devices. Various conventional solutions are provided to reduce the consumption of energy but most methods focus on increasing the data acquisition speed, data transmission and routing capabilities. However, these methods tend to fall under the trade-off between these three factors. Hence, in order to maintain the trade-off between these constraints, a viable solution is developed in this paper. A deep learning-based routing is built considering the faster acquisition of data, faster data transmission and routing path estimation with increasing path estimation. The paper models a Deep belief Network (DBN) to route the data considering all these constraints. The experimental validation is conducted to check the network lifetime, energy consumption of IoT nodes. The results show that the DBN offers greater source of flexibility with increased data routing capabilities than other methods.

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“…The work from [2] improves this idea by predicting the actual locations of the DRC violations, using a different set of features. Finally, the work from [17] focuses on predicting only the existence of detailed routing short violations, so that this information can be used in a detailed placement flow, for example. Although different works make use of machine learning techniques, none of them aim to predict the quality of legalization algorithms, which is the focus of this work.…”

Section: Related Workmentioning

confidence: 99%

“…The high flexibility provided by machine learning (ML) models allows their use to predict the outcome of physical design algorithms. They have been employed so far to help choose between different clock tree synthesis algorithms [11], to fix miscorrelations between different timing engines [7], and to identify detailed routing violations during the placement stage [2,17,19]. The benefits of ML models come from their ability to improve the quality of physical design algorithms by predicting information that would otherwise be too costly to evaluate during execution.…”

Section: Introductionmentioning

confidence: 99%

How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization

Netto

Fabre

Fontana

et al. 2019

Proceedings of the 2019 International Symposium on Physical Design

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Machine learning has been used to improve the predictability of different physical design problems, such as timing, clock tree synthesis and routing, but not for legalization. Predicting the outcome of legalization can be helpful to guide incremental placement and circuit partitioning, speeding up those algorithms. In this work we extract histograms of features and snapshots of the circuit from several regions in a way that the model can be trained independently from region size. Then, we evaluate how traditional and convolutional deep learning models use this set of features to predict the quality of a legalization algorithm without having to executing it. When evaluating the models with holdout cross validation, the best model achieves an accuracy of 80% and an F-score of at least 0.7. Finally, we used the best model to prune partitions with large displacement in a circuit partitioning strategy. Experimental results in circuits (with up to millions of cells) showed that the pruning strategy improved the maximum displacement of the legalized solution by 5% to 94%. In addition, using the machine learning model avoided from 22% to 99% of the calls to the legalization algorithm, which speeds up the pruning process by up to 3×.

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A machine learning framework to identify detailed routing short violations from a placed netlist

Cited by 29 publications

References 20 publications

Congestion Prediction in FPGA Using Regression Based Learning Methods

Congestion Prediction in FPGA Using Regression Based Learning Methods

Network Lifetime Analysis in IOT Environment in Healthcare Sectors Using Deep Learning Routing Approach

How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization

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