A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range

Kandpal, Naveen; Singh, Anil; Agarwal, Alpana

doi:10.1007/s00034-022-02001-x

Cited by 6 publications

(9 citation statements)

References 44 publications

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“…Learning how conversion gain, noise figure, linearity, and isolation are impacted in topologies and under operating conditions, while constantly learning from and improving the datasets can lead to improved performance, as reported by [16], [34], and [35]. As with feedback and control systems, AI-assisted mixers also require large and accurate datasets that may be difficult and time-consuming to generate.…”

Section: B Mixermentioning

confidence: 99%

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Analog and Mixed-signal Integrated Circuits of 5Gand 6G Data Communication

2024

IJFMR

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The complex analog and mixed-signal transceivers where overall system performance is often limited by the weakest performing subsystem. While analog and mixed-signal integrated circuits have significantly advanced, the future of 5G and 6G transceiver design could be accelerated by including artificial intelligence. In this combination, analog integrated circuit design and operation would harness machine learning to identify, characterize, and act upon variations and anomalies in system performance. Focusing on 5G and 6G, this paper investigates solutions for a unified intelligent integrated transceiver: a conceptual combination of a traditional analog subsystem, a supporting digital subsystem that enables artificial intelligence, and dedicated feedback circuitry or sensors that monitor performance, efficiency, or reliability. Active and passive components and propagation channels are reviewed based on their merits of introducing intelligence. Holistically and for broader applicability, the paper conceptualizes and coins the notion of an ‘‘intelligent integrated system (IIS)’’, which brings forward a novel unified vision and approach toward context-aware subsystems that dynamically interact with ambient and varying operating conditions. To demonstrate viability, the paper concatenates a select set of measurement results.

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Section: B Mixermentioning

confidence: 99%

“…In [35], VCOs are designed with high linearity and a wide tuning range by using neural networks to optimize the design. The Mamyshev oscillator cavity, which can produce high-energy ultrashort pulses based on the PSO algorithm is proposed in [37].…”

Section: Frequency Synthesizermentioning

confidence: 99%

Analog and Mixed-signal Integrated Circuits of 5Gand 6G Data Communication

2024

IJFMR

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“…Adding intelligence to these topologies may result in a time and cost reduction for designers. An ML technique for VCO design is proposed in [37]. The proposed VCO is process, voltage, and temperature (PVT) robust and has an expanded linearity range.…”

Section: Frequency Synthesizermentioning

confidence: 99%

“…In addition, the potential for automated design optimization and parameter extraction from this method is discussed in [40]. [37] presents a promising method for resolving the challenge of parasitic modeling and extraction verification in IC design using neural networks.…”

Section: Frequency Synthesizermentioning

confidence: 99%

Intelligent Integrated Circuits and Systems for 5G/6G Telecommunications

Lambrechts,

Sinha,

Sengupta

et al. 2024

IEEE Access

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Millimeter-wave and Terahertz communications consist of complex analog and mixed-signal transceivers where overall system performance is often limited by the weakest performing subsystem. While analog and mixed-signal integrated circuits have significantly advanced, the future of 5G and 6G transceiver design could be accelerated by including artificial intelligence. In this combination, analog integrated circuit design and operation would harness machine learning to identify, characterize, and act upon variations and anomalies in system performance. Focusing on 5G and 6G, this paper investigates solutions for a unified intelligent integrated transceiver: a conceptual combination of a traditional analog subsystem, a supporting digital subsystem that enables artificial intelligence, and dedicated feedback circuitry or sensors that monitor performance, efficiency, or reliability. Active and passive components and propagation channels are reviewed based on their merits of introducing intelligence. Holistically and for broader applicability, the paper conceptualizes and coins the notion of an "intelligent integrated system (IIS)", which brings forward a novel unified vision and approach toward context-aware subsystems that dynamically interact with ambient and varying operating conditions. To demonstrate viability, the paper concatenates a select set of measurement results.

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“…This is achieved by first detecting the slope m D,desired of the ADC transfer curve by using a slope detector. 29 Also, this m D,desired slope in the range where it is more linear is obtained using the linear range detector block.…”

Section: Proposed Adc Architecturementioning

confidence: 99%

An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate

Kandpal,

Singh,

Agarwal

2024

Circuit Theory & Apps

Self Cite

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This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is μm2.

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A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range

Cited by 6 publications

References 44 publications

Analog and Mixed-signal Integrated Circuits of 5Gand 6G Data Communication

Analog and Mixed-signal Integrated Circuits of 5Gand 6G Data Communication

Intelligent Integrated Circuits and Systems for 5G/6G Telecommunications

An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate

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